A test generation method with broadcast for built-in self-test (BIST) is proposed to solve problems of power consumption,hardware overhead and large test data volume in chip testing.The hardware implementation and test scheme of the method are given.Multiple singleinput change (MSIC) sequences are generated by an XOR network that combines a linear feedback shift register (LFSR) structure with a Johnson counter.Then,the broadcast circuit expands the MSIC sequences to broadcast-based multiple single input change (BMSIC) test patterns that are able to fill more scan chains,so that the hardware overhead of the test pattern generation circuit is reduced.Simulation results with ISCAS'89 benchmarks and a comparison with the MSIC test pattern generation circuit shows that the proposed BMSIC test method reduces the circuit hardware overhead about 50％ with ensuring of low power consumption and high fault coverage.%针对半导体器件特征尺寸小、集成电路集成度和复杂度高导致的芯片测试功耗高、面积开销和测试数据量大等问题,提出了一种带广播结构的低功耗低成本内建自测试的测试图形生成方法,给出了硬件实现方式和测试方案.首先,该方法通过一个异或网络将线性反馈移位寄存器(LFSR)结构和Johnson计数器相结合,产生具有多维单输入跳变(MSIC)特性的测试向量;然后,通过复用测试生成结构,广播电路将测试向量扩展为能够填充更多扫描链的基于广播的多维单输入跳变(BMSIC)测试图形,从而减小了测试图形生成电路的面积开销;最后,以ISCAS'89系列中较大的5款电路为对象实验,结果表明,与MSIC测试生成电路相比,BMSIC测试图形生成方法可在确保低功耗高故障覆盖率基础上,减小50％左右的电路面积开销.
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