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内进化容错模型设计及其可靠性分析

         

摘要

仿照自然界的碳基生物进化过程,在FPGA内部实现了可控的硅基进化。针对电子系统常见的SA故障,提出了基于演化硬件技术的内进化容错模型,通过在FPGA内部装载Microblaze CPU和构建可重配置阵列,实现了演化硬件的片内进化。利用该模型进行了故障容错实验,检验了其有效的故障容错能力,证明该容错方法能够有效提高数字电路的可靠性。%The controllable silicon evolution was realized inside FPGA by imitating evolution process of the carbon-based biologies in the natural world. According to the common SA faults in electronic systems,an intrinsic evolvable fault-tolerant mod-el based on evolution of hardware technology is proposed. Through loading Microblaze CPU inside FPGA and establishing recon-figurable arrays,the evolution-in-chip of evolvable hardware was implemented. Fault tolerance experiment was done to test the capability of fault-tolerance by the model. The experimental result shows that method can effectively improve the reliability of dig-ital circuits.

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