基于新一代图像压缩国际标准JPEG 2000,介绍一种快速、有效的多层5/3小波变换的VLSI设计结构,该方法使用两组一维变换实现,用移位一相加代替乘法操作,整体设计采用了流水线设计.利用双端口RAM和地址生成模块的调度完成小波变换的分裂、边界延拓工作,不需另外增加模块.二维离散小波变换滤波器结构的设计采用Veri1og HDL进行RTL级描述,已经通过了FPGA验证,并可作为单独的IP核应用于图像编解码芯片中.%On the basis of JPEG 2000, a new generation of image compression standard, a new type of structure introducing the both high efficient and rapid VLSI with the multi-layer 5/3 wavelet transform is presented. It is realized by two groups of one-dimension transform and operated by phase adding instead of multiplication. The pipeline design is adopted in the entire design. Thedual-port RAM and the scheduling of an address generation module are employed to achieve the split of wavelet transform and boundary extension without any module addition. Verilog HDL is utilized to perform RTL level description in the whole design for two-dimension discrete wavelet transform filtering structure. It was verified by FPGA. It can be applied to the development of image decoding ehip as an independent IP core.
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