采用TSMC 0.18 μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器(ADC).为了减小失真和降低功耗,该ADC利用余量增益放大电路(MDAC)内建的采样保持功能.去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性.使用Cadeace Spectre对电路进行仿真.结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB.当输入频率为50 MHz的信号时,SFDR依然有80.51 dB.使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW.%A 12-bit 50 MS/s CMOS pipelined A/D converter(ADC) is presented. This ADC is implemented in the TSMC 0. 18 μm 1P6M CMOS process. In this circuit, the traditional sample and hold module is totally removed by taking advantage of the inherent sample and hold function of multiplying DAC( MDAC) to reduce power consumption and distortion. In order to maintain good linearity when input is high frequency signal, this ADC employs time-constant matching techniques. Meanwhile, digital calibration technique helps ADC to be less sensitive to comparator offset. The A/D converter is simulated by Cadence Spectre. The result shows that the converter achieves an SNDR of 72. 19 dB and an SFDR of 88. 23 dB at Nyquist input. It still maintains an SFDR of 80. 51 dB at 50 MHz input At 50MHz sampling rate, this ADC consumes 128 mW from a 1.8 V supply.
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