Optimization of Knowledge Base is key and difficulty to improve the performance of fuzzy control. This paper adjusts and optimizes the inference rules of proportionality and integral coefficient of fuzzy PID controller by combining the theory analysis with conventional inference rules. Then it was tested on the simu-lation platform of MATLAB/SIMULINK. And it proves that the optimized controller has better robustness and adaptability than the previous one. For a typical second order system with a step input, the rise time and peak time was both reduced by 8ms, the overshoot by 2. 18% and the setting time( ± 5% ) by 105ms which is vital in the occasions containing high frequency disturbance and frequent changes of the parameters. Meanwhile, the Fuzzy self-turning PID IP (Intellectual Property) Core based on FPGA(Field Programmable Gate Array) was implemented by using Verilog HDL and modular design method, to make it be flexibly used in system de-sign based on SOPC (System on Programmable Chip). In this core designing, the modified incremental PID algorithm was used, and the part of fuzzy self-turning was replaced by on-line look-up table structure and off-line inference, thus simplifying this design and reducing the hardware resources. The simulation results shows that the IP core can achieve correct and effective results and can be flexibly called.%优化知识库是提高模糊控制性能的关键和难点,文章结合传统模糊PID控制规则与理论知识,重点优化了比例系数和积分系数的推理规则,并在Matlab/Simulink仿真平台进行验证。优化后的控制器具有更强的适应性和鲁棒性,对于典型二阶系统,在阶跃输入条件下,上升时间与峰值时间均减少8ms,超调量下降2.18%,进入±5%误差带调整时间减少105ms,在高频扰动或被控参数变化频繁的场合尤其重要。同时,为使该控制器灵活运用于SOPC系统级设计,文章运用Verilog HDL描述语言,采用模块化设计方法,模糊推理部分采用离线计算、在线查表的方式,PID算法采用改进的增量式并行结构,实现了基于FPGA的模糊自适应PID控制器IP软核,简化了系统设计,降低了FPGA资源耗费。测试结果表明,该控制器IP软核结果正确有效,可以灵活调用。
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