随着时代的发展，计算机已经得到了广泛的应用，并逐渐成为人们生产生活中不可或缺的部分。单核处理器，由于其内部结构和频率功耗等因素的影响，已无法满足人们对处理器的要求，所以，多核处理器、众核处理器应运而生。本文针对众核处理器核间通信的现有结构特点—数据等待、每个核负担大、功耗大等缺点，提出了一种适应于异构众核处理器的核间通信结构—总线中间缓存（B-MM）结构，大幅度减少核间通信的等待情况，并且尽可能的简化每一个核的内部结构使其功能专一，提高其工作效率，进而提高众核处理器的性能。最后通过Modelsim SE仿真平台实验，验证了其可行性。%With the development of the times, the computer has been widely used, and gradually becomes an integral part of production and life. Single-core processor, due to its internal structure and frequency consumption and other factors, has been unable to meet the requirements of the people to the processor, so that multi-core processors and many-core processor came into being. For the shortcomings of the structural characteristics of inter-core communications of many-core processor, such as, data latency, big load of each core, large power consumption and son on, this paper proposes the B-MM structure which can adapt to the heterogeneous many-core processor to significantly reduce the data latency of inter-core communications and as far as possible to simplify the internal structure of each core, improve their working efficiency, and improve the performance of many-core processors, and finally tests its feasibility through Modelsim SE simulation platform experiment.
展开▼
