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VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

机译:具有路由和事件排序功能的基于2.8 Gevent / s数据包的AER接口的VLSI实现

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摘要

State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.
机译:最新的大型神经形态系统需要神经网络各单元之间的复杂的尖峰事件通信。我们基于在现场可编程门阵列(FPGA)维护的环境中的专用神经形态通信IC,为晶圆级神经形态系统提供了一种高速通信基础设施。这些IC实现了某些类型的动态处理或在遥远的皮质区域之间模拟基于尖峰的学习所需的可配置的轴突延迟。提出了测量结果,这些测量结果显示了这些延迟对神经形态基准行为的影响。在大多数当前系统中,专用的专用地址事件表示通信需要单独的低带宽配置通道。相比之下,晶圆级神经形态系统的配置也由基于数字数据包的脉冲通道处理,该通道以全带宽传输配置数据,否则将其用于脉冲传输。总体而言,所谓的脉冲通信子组(IC和FPGA)比其他当前的神经形态通信基础设施提供25–50倍的事件传输速率。

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