Efficient approaches to low-cost high-fault coverage VLSI BIST designs

Chen C.-I.H.

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Efficient approaches to low-cost high-fault coverage VLSI BIST designs

机译：低成本，高故障覆盖率的VLSI BIST设计的有效方法

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This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead.

机译：这项工作介绍了一种内置的自测（BIST）设计方法，该方法可以依次测试具有很高故障覆盖率的大型超大规模集成（VLSI）电路。所建议的技术，即循环BIST（（BIST）和（带有伪部分扫描的BIST（PPSCAN）），是根据循环自测路径（CSTP）的原理建模的，该方法的基础是要以最小的硬件开销增加为代价结果表明，与现有的顺序测试方法相比，该技术在合理的时间和测试矢量长度下具有更高的故障覆盖率，并通过在实际VLSI电路中的应用证明了该技术的有效性。，包括：1）MIPS 3000中央处理器（CPU）核心的系统控制协处理器（CP0），以及2）SIMD图形引擎，即增强型存储芯片（EMC）。 BIST结果表明（BIST及其派生（带有伪部分扫描的BIST（PPSCAN））对于实际的VLSI设计是可行的，并且生成具有高故障覆盖率和低开销的BIST。

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《IEEE Transactions on Aerospace and Electronic Systems》 |1998年第1期|P.63-70|共8页
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Chen C.-I.H.;
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1. Efficient approaches to low-cost high-fault coverage VLSI BISTdesigns [J] . Chen C.-I.H. IEEE Transactions on Aerospace and Electronic Systems . 1998,第1期

机译：低成本，高故障覆盖率的高效方法VLSI BISTdesigns
2. Circular self-test path: a low-cost BIST technique for VLSI circuits [J] . Krasniewski A., Pilarski S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1989,第1期

机译：循环自检路径：用于VLSI电路的低成本BIST技术
3. VLSI implementation of an efficient MBIST architecture using RLFSR [J] . Omanakuttan Sheela Nisha, K. Siva Sankar International journal of systems,control and communications . 2020,第3期

机译：VLSI使用RLFSR实现有效的MBist架构
4. Novel approaches to low leakage and area efficient VLSI design [C] . Izma Tajrian, Barua Parag, Rahman Md. Rejaur, 2012 International Conference on Informatics, Electronics amp; Vision. . 2012

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5. Power efficient design of SRAM arrays and optimal design of signal and power distribution networks in VLSI circuits [D] . Amelifard, Behnam 2007

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8. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design [R] . Trotter, J. D., Naini, A. K. R. 1985

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Efficient approaches to low-cost high-fault coverage VLSI BIST designs

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