Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

Cerny C.L.; Via G.D.

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Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

机译：Xs-MET-使用互补异质结场效应晶体管的模拟，低功耗，空间应用的复杂性降低的制造工艺

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The requirements for space-based integrated circuit applications are defined with an emphasis on being radiation tolerant and low power consuming. Flexible analog signal processors (FASPs) are outlined as a means by which effective circuit designs can be utilized to perform a multitude of tasks. The development of complementary III-V technologies have been proven to meet the demands of the space environment, and have demonstrated the potential for frequency operation beyond 1 GHz using power supply voltages at or below 1.5 Volts. The novel fabrication process known as Xs-MET (pronounced kismet, which uses the Creek letter chi, X, and stands for Complementary Heterostructure Integrated Single Metal Transistor), is introduced as a manufacturing technique to be used in FASP design. The Xs-MET fabrication process is outlined with preliminary device results presented. An example of a FASP circuit design using Xs-MET is provided. Conclusions regarding the utilization of the Xs-MET process for FASPs are outlined with comments focusing on a space-based demonstration.

机译：定义了基于空间的集成电路应用的要求，重点是耐辐射和低功耗。概述了灵活的模拟信号处理器（FASP）作为一种手段，通过该手段可以利用有效的电路设计来执行多种任务。事实证明，补充性III-V技术的发展可以满足太空环境的需求，并且已经证明使用1.5伏或更低的电源电压可以在1 GHz以上的频率下运行。作为FASP设计中使用的制造技术，介绍了一种称为Xs-MET的新颖制造工艺（发音为kismet，它使用Creek字母chi，X，并表示互补异质结构集成单金属晶体管）。概述了Xs-MET的制造过程，并提供了初步的器件结果。提供了使用Xs-MET的FASP电路设计的示例。概述了有关将Xs-MET工艺用于FASP的结论，并重点关注了基于空间的演示。

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《IEEE Aerospace and Electronic Systems Magazine》 |1998年第3期|P.7-14|共8页
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Cerny C.L.; Via G.D.;
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1. Xs-MET-a reduced complexity fabrication process using complementaryheterostructure field effect transistors for analog, low power, spaceapplications [J] . Cerny C.L., Via G.D., Ebel J.L., IEEE Aerospace and Electronic Systems Magazine . 1998,第3期

机译：Xs-MET-使用互补异质结构场效应晶体管降低复杂性的制造工艺，适用于模拟，低功耗，空间应用
2. Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier [J] . Varsha S. Bendre, A. K. Kureshi, Saurabh Waykole Journal of nanotechnology . 2018,第期

机译：基于碳纳米管场效应晶体管的低功率折叠式共源共栅运算放大器的模拟信号处理应用设计
3. Design of Analog Signal Processing Applications Using Carbon Nanotube Field Effect Transistor-Based Low-Power Folded Cascode Operational Amplifier [J] . Varsha S. Bendre, A. K. Kureshi, Saurabh Waykole Journal of nanotechnology . 2018,第5期

机译：基于碳纳米管场效应晶体管的低功率折叠式共源共栅运算放大器的模拟信号处理应用设计
4. Xs-MET, a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications [C] . Cerny, C., Via, . 1997

机译：Xs-MET，一种复杂度降低的制造工艺，使用互补异质结构场效应晶体管进行模拟，低功耗，空间应用
5. Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization. [D] . Mookerjea, Saurabh A. 2010

机译：适用于低功耗逻辑和存储器应用的带间隧穿场效应晶体管：设计，制造和表征。
6. Robust In-Zn-O Thin-Film Transistors with aBilayer Heterostructure Design and a Low-Temperature Fabrication ProcessUsing Vacuum and Solution Deposited Layers [O] . Sang Yun Bang, Felix C. Mocanu, Tae Hoon Lee, 2020

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7. A Novel Carbon Nanotube Field Effect Transistor based Arithmetic Computing Circuit for Low-power Analog Signal Processing Application [O] . sankar P.A. Gowri, Udhayakumar K. 2014

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8. Complementary GaAs junction-gated heterostructure field effect transistor fabrication for integrated circuits [R] . Baca, A. G. , Zolper, J. C. , Sherwin, M. E. , 1994

机译：用于集成电路的互补Gaas结栅控异质结构场效应晶体管制造

Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

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