• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>American journal of applied sciences >Spartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay Study
【24h】

Spartan-3AN Field Programmable Gate Arrays Truncated Multipliers Delay Study

机译：Spartan-3AN现场可编程门阵列截断乘法器延迟研究

获取原文
获取原文并翻译 | 示例
       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Problem statement: The image processing applications, such as MPEG video compression used in CT scan frames requires real time conditions and the algorithms should be verified and optimized before implementation which cannot be done with Application Specific Integrated Circuits (ASICs) because they are not reconfigurable and cost is very high. Approach: The FPGA is a viable technology that could be implemented and reconfigured at the same time, since FPGA have the benefit of hardware speed and the flexibility of software. Results: The results obtained from Sparatn-3An FPGA showed the mean delay time for four multipliers, clearly indicates as the size of multiplier increases the mean delay time also increases. Conclusion: The FPGA based truncated multipliers could also be used in medical imaging technology.
机译：问题陈述：图像处理应用程序（例如，CT扫描帧中使用的MPEG视频压缩）需要实时条件，并且应在实现之前对算法进行验证和优化，这是专用集成电路（ASIC）无法完成的，因为它们不可重新配置且成本很高。方法：FPGA是一项可行的技术，可以同时实现和重新配置，因为FPGA具有硬件速度和软件灵活性的优势。结果：从Sparatn-3FPGA获得的结果显示了四个乘法器的平均延迟时间，清楚地表明，随着乘法器大小的增加，平均延迟时间也会增加。结论：基于FPGA的截断乘法器也可用于医学成像技术。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号