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首页> 外文期刊>Applied Physics >Temperature and SiO_2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs
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Temperature and SiO_2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs

机译：温度和SiO_2 / 4H-SiC界面陷阱对低击穿电压MOSFET的电学特性的影响

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摘要

The temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal-oxide-semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (V-th), channel mobility (mu(ch)), and on-state resistance (R-ON) are calculated in the temperature range of 300K to 500K starting from the device current-voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H-SiC interface traps act to increase R-ON, reduce mu(ch), and increase the sensitivity of V-th with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining R-ON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2V(th) (i.e., V-GS12V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the R-ON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences V-th (negative shifting) and penalizes the device drain current over the whole explored voltage range.
机译：研究了温度和载流子陷阱对尺寸为低击穿电压（BVDS）的4H碳化硅（4H-SiC）金属氧化物半导体场效应晶体管（MOSFET）的电特性的影响。首先，参照新鲜的设备（无缺陷）评估温度的影响。具体地，从器件电流-电压特性开始，在300K至500K的温度范围内计算阈值电压（V-th），沟道迁移率（mu（ch））和导通电阻（R-ON）。然后考虑有缺陷的MOSFET。参考文献数据，考虑了4H-SiC带隙（深部和尾部中心）和氧化物固定阱中缺陷能级的组合模型。仿真结果表明，SiO2 / 4H-SiC界面陷阱可提高R-ON，减小mu（ch）并随温度提高V-th的灵敏度。更详细地讲，一旦引入尾部陷阱的贡献，中间能隙中的深层陷阱在确定R-ON方面的作用有限。同样，对于大于2V（th）的栅极偏置（即V-GS> 12V），反型层中移动载流子的增加导致陷阱的屏蔽增加，从而增强了MOSFET的输出电流，从而限制了R-ON的增加。特别是在低温下。最后，高的氧化物固定阱密度会显着影响Vth（负漂移），并在整个探索的电压范围内损害器件的漏极电流。

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  • 来源
    《Applied Physics》 |2019年第5期|294.1-294.10|共10页
  • 作者

    Bencherif H.; Dehimi L.; Pezzimenti F.; Della Corte F. G.;

  • 作者单位

    Univ Biskra, LMSM, Biskra, Algeria|Univ Mostefa Benboulaid, LAAAS, Batna 2, Algeria;

    Univ Biskra, LMSM, Biskra, Algeria;

    Mediterranea Univ Reggio Calabria, DIIES, Reggio Di Calabria, Italy;

    Mediterranea Univ Reggio Calabria, DIIES, Reggio Di Calabria, Italy;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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