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Influence of Si wafer thinning processes on (sub)surface defects

机译：硅晶片减薄工艺对（亚）表面缺陷的影响

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Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of mu m. Here, we expand the characterization of Si (sub)surface to 5 mu m thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 mu m. For the case of Si thinning towards 5 pin using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 mu m. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding+ CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface. (C) 2017 Elsevier B.V. All rights reserved.
机译：具有最小Si厚度的晶片到晶片的三维（3D）集成可以产生相互作用的具有显着缩放的垂直互连的多个器件。然而，实现这种薄的3D结构关键取决于薄化工艺之后剩余的背面Si的表面和亚表面。机械研磨后的Si（亚）表面的特征已经达到数十微米的有效结果。在这里，我们在介电键合晶片上进行减薄工艺后，将Si（亚）表面的特性扩展到5μm厚度。在研磨，化学机械抛光（CMP），湿法蚀刻和等离子干法蚀刻之后，研究了表面缺陷和损伤层。使用透射显微镜，原子力显微镜和正电子an没光谱对（亚）表面缺陷进行表征。尽管研磨提供了最快的Si去除率，但表面粗糙度与后续处理不兼容。此外，无论Si厚度和薄晶圆处理系统如何，都无法减少诸如位错和非晶Si之类的机械损伤。即使去除量为1μm，研磨后的CMP也表现出优异的去除该研磨损伤的性能。对于使用研磨和CMP将Si细化到5针的情况，（子）表面是没有空位的粗糙度的原子尺度。对于研磨+干蚀刻的情况，在0.5-2μm左右的表面下检测到空位缺陷。湿法蚀刻后的成品表面在应变区域内保持在纳米级。通过在研磨和干蚀刻之间插入CMP步骤，不仅可以显着降低粗糙度，而且还可以显着降低表面下的剩余空位。研磨+ CMP +干蚀刻的表面产生与研磨+ CMP相同的单空位结果。减薄工艺的这种组合允许开发具有最小粗糙度和空缺表面的极薄3D集成设备。 （C）2017 Elsevier B.V.保留所有权利。

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