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首页> 外文期刊>Applied Surface Science >Elimination of GeO_2 and Ge_3N_4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates
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Elimination of GeO_2 and Ge_3N_4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

机译：消除GeO_2和Ge_3N_4界面过渡区域以及n型Ge界面处的缺陷：在Ge衬底上形成n-MOS器件的途径

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摘要

The contribution from relatively low-K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness (EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of significant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface.
机译：Si和过渡金属（TM）栅极电介质之间的相对低K的SiON界面过渡区（ITR）的贡献严重限制了Si互补金属氧化物半导体（CMOS）器件的等效氧化物厚度（EOT）缩放比例。该限制同样重要，并且对Ge CMOS器件也有限制。 Ge器件中的基于低K Ge的ITR也已显示出会限制性能和可靠性，特别是对于n-MOS场效应晶体管。本文确定了在n-Ge或反向p-Ge与Ge氧化物，氮化物和氮氧化物ITR之间的界面处大量电子陷阱的来源。这被证明是一个界面能带对准问题，其中天然Ge ITR的导带偏移能量小于TM电介质的能带偏移能量，并且俘获电子以实现负Ge衬底偏置。本文还介绍了一种新颖的远程等离子体处理方法，该方法可有效消除任何重要的天然Ge ITR，并使用等离子体处理/退火工艺序列将TM栅极电介质直接粘合到Ge衬底表面。

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