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首页> 外文期刊>Arabian Journal for Science and Engineering. Section A, Sciences >An 8-Bit Unified Segmented Current-Steering Digital-to-Analog Converter
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An 8-Bit Unified Segmented Current-Steering Digital-to-Analog Converter

机译：一个8位统一分段电流转向数模转换器

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摘要

In this paper, an 8-bit segmented current-steering digital-to-analog converter (DAC) is presented where the digital and analog parts are unified using current mode binary to thermometer decoder, resulting in a smaller chip area and simple layout scheme. In addition, the latch and driver circuits which are the main blocks of conventional currentsteeringDACs are eliminated in this design. Thus, the number of transistors in the digital part of DAC is reduced and higher sampling rate is obtained. Furthermore, the proposed current mode decoder has lower output voltage variation and consequently lower dynamic power dissipation. Finally, the proposed DAC is simulated in 0.18μm CMOS technology with the 1.8V supply voltage. The post-layout simulation results show that differential nonlinearity and integral nonlinearity errors are 0.034 and 0.024LSB, respectively. In addition, the spurious-free dynamic range is 51dB over 94MHz output bandwidth at 500 MS/s. Moreover, the total power dissipation of the designed DAC is only 5.7mW and the active area is small equal to 0.02mm~2.
机译：在本文中，介绍了一个8位分段的电流转向数字转换数字转换器（DAC），其中使用电流模式二进制文件到温度计解码器统一，导致芯片区域和简单的布局方案统一。另外，在这种设计中消除了作为传统的CurrentSeeRingdacs主块的锁存器和驱动电路。因此，降低了DAC的数字部分中的晶体管的数量，并且获得了更高的采样率。此外，所提出的电流模式解码器具有较低的输出电压变化，从而降低动态功耗。最后，提出的DAC以0.18μm的CMOS技术模拟，具有1.8V电源电压。后布局仿真结果表明，差分非线性和整体非线性误差分别为0.034和0.024LSB。此外，无杂散的动态范围为51dB超过94MHz输出带宽，500 ms / s。此外，设计的DAC的总功耗仅为5.7mW，活动区域小于0.02mm〜2。

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