A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

Yueh Wen; Chatterjee Subho; Zia Muneeb; Bhunia Swarup; Mukhopadhyay Saibal

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A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

机译：基于存储器的逻辑块，具有针对读取优化的SRAM，用于节能型可重配置计算架构

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摘要

A memory-based logic block (MLB), which is a building block for memory-based reconfigurable computing framework, is presented in 130-nm CMOS. The MLB is designed with an optimized-for-read (OFR) 6T static random access memory (SRAM)-based lookup table and demonstrates single- and multicycle evaluation of complex functions. Power-aware mapping leverages the data-dependent read power of the OFR SRAM to reduce MLB evaluation power.

机译：基于内存的逻辑块（MLB）是基于内存的可重配置计算框架的构建块，以130 nm CMOS呈现。 MLB设计有基于优化读取（OFR）的6T静态随机存取存储器（SRAM）的查找表，并演示了复杂功能的单周期和多周期评估。功耗感知映射利用了OFR SRAM的数据相关读取能力来降低MLB评估能力。

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《Circuits and Systems II: Express Briefs, IEEE Transactions on》 |2015年第6期|593-597|共5页
作者
Yueh Wen; Chatterjee Subho; Zia Muneeb; Bhunia Swarup; Mukhopadhyay Saibal;
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正文语种 eng
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关键词
Memory-based computing; Static Random Access Memory; memory based computing; reconfigurable hardware; static random access memory (SRAM);

机译：基于内存的计算;静态随机存取存储器;基于内存的计算;可重新配置的硬件;静态随机存取存储器（SRAM）;

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1. Reconfigurable logic in nanosecond Cu/GeTe/TiN filamentary memristors for energy-efficient in-memory computing [J] . Jin Miao-Miao, Cheng Long, Li Yi, Nanotechnology . 2018,第38期

机译：用于节能内存计算的纳秒Cu / Gete / TiN丝雾滤网中的可重新配置逻辑
2. A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks [J] . Masatoshi NAKAMURA, Masato INAGI, Kazuya TANIGAWA, IEICE transactions on information and systems . 2012,第2期

机译：一种不带开关块的新的基于内存的可重配置体系结构的物理设计方法
3. A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks [J] . Masatoshi NAKAMURA, Masato INAGI, Kazuya TANIGAWA, IEICE Transactions on Information and Systems . 2012,第2期

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4. A tunnel-FET SRAM array for energy-efficient embedded memory blocks in reconfigurable computing platforms [C] . Amir M.F., Trivedi A.R., Mukhopadhyay S. SOI-3D-Subthreshold Microelectronics Technology Unified Conference . 2014

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5. Parallelizing matrix -oriented computing applications on reconfigurable computing fabrics: Methodology and architecture. [D] . Akella, Sreesa. 2006

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6. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process [O] . Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, 2017

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7. Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing [O] . Abbas Rahimi, Amirali Ghofrani, Miguel Angel Lastras-montano, 2015

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A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric

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