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Design of a New Serializer and Deserializer Architecture for On-Chip SerDes Transceivers

机译：片上SerDes收发器的新型串行器和解串器架构的设计

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摘要

The increasing trends in SoCs and SiPs technologies demand integration of large numbers of buses and metal tracks for interconnections. On-Chip SerDes Transceiver is a promising solution which can reduce the number of interconnects and offers remarkable benefits in context with power consumption, area congestion and crosstalk. This paper reports a design of a new Serializer and Deserializer architecture for basic functional operations of serialization and deserialization used in On-Chip SerDes Transceiver. This architecture employs a design technique which samples input on both edges of clock. The main advantage of this technique which is input is sampled with lower clock (half the original rate) and is distributed for the same functional throughput, which results in power savings in the clock distribution network. This proposed Serializer and Deserializer architecture is designed using UMC 180 nm CMOS technology and simulation is done using Cadence Spectre simulator with a supply voltage of 1.8 V. The present design is compared with the earlier published similar works and improvements are obtained in terms of power consumption and area as shown in Tables 1-3 respectively. This design also helps the designer for solving crosstalk issues.
机译：SoC和SiP技术的不断增长的趋势要求集成大量的总线和用于互连的金属轨道。片上SerDes收发器是一种很有前途的解决方案，它可以减少互连数量，并在功耗，面积拥塞和串扰的背景下提供显着的优势。本文报告了一种新的串行器和解串器体系结构的设计，该体系结构用于片上SerDes收发器中的串行化和反序列化的基本功能操作。该架构采用了一种设计技术，该技术对时钟的两个边沿上的输入进行采样。这种输入技术的主要优点是使用较低的时钟（原始速率的一半）进行采样，并以相同的功能吞吐量进行分配，从而节省了时钟分配网络中的功耗。该拟议的串行器和解串器体系结构是使用UMC 180 nm CMOS技术设计的，并且使用Cadence Spectre模拟器在1.8 V的供电电压下进行了仿真。将本设计与早期发布的类似作品进行了比较，并在功耗方面取得了改进和面积分别如表1-3所示。这种设计还可以帮助设计人员解决串扰问题。

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  • 来源
    《Circuits and systems》 |2015年第3期|81-92|共12页
  • 作者

    Nivedita Jaiswal; Radheshyam Gamad;

  • 作者单位

    Department of Electronics and Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India;

    Department of Electronics and Instrumentation Engineering, Shri G. S. Institute of Technology and Science, Indore, India;

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  • 原文格式 PDF
  • 正文语种 eng
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  • 关键词

    SerDes Transceiver; Serializer; Deserializer; SoC; Cadence;

    机译：SerDes收发器;序列化器解串器;SoC;韵律;

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