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A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology

机译：深亚微米技术的新型高性能耐泄漏，宽扇入Domino逻辑电路

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摘要

As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27℃ with C_L = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.
机译：随着现代技术的萎缩，微处理器中对高速，低功耗和小芯片面积的需求已经出现。在本文中，我们提出了一种新型的多米诺骨牌电路设计，以实现低功耗，更快的电路速度和高性能。由于广泛的扇入多米诺骨牌逻辑，其逻辑门会受到噪声灵敏度的影响，如果我们提高灵敏度，则亚阈值和栅极氧化物泄漏电流将在评估网络中占主导地位，这会增加功耗并降低电路性能。拟议中的电路改善了动态功耗并减少了延迟，从而提高了电路速度。该仿真是在BISM4 Cadence环境中以65 nm工艺技术进行的，在100 MHz频率下电源电压为1 V，C_L的瓶颈工作温度为27℃ = 1 fF。从结果来看，拟议的电路1和2对8个输入或门的平均功率改善为10.1％，15.28％SFLD，48.56％，51.49％CKD，55.17％，57.71％HSD，延迟改善为1.10％，12.76％SFLD， DFD分别为19.13％，28.63％CKD，4.32％，15.59％HSD，19.138％和44.25％。

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