An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

Ananthanarayanan Parthasarathy

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An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

机译：基于65 nm CMOS的8位0.8 GS / s 8.352 mW修改型基于逐次逼近寄存器的模数转换器

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We propose a new approach in reducing the power consumption of the successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB)-7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65 nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25 fJ/step.

机译：我们提出了一种通过更改SAR-ADC的数模转换器（DAC）输入的收敛算法来降低逐次逼近寄存器模数转换器（SAR-ADC）功耗的新方法。设计并分析了不同的搜索算法，例如二进制搜索树，移动二进制搜索树（BST），最低有效位移位器（LSB），自适应算法和拆分寄存器移动BST算法，以加快DAC输入的收敛速度。设计了一个0.8 GS / s，8位（有效位数（ENOB）-7.42），8.552 mW SAR ADC，并采用了建议的65 nm CMOS移动BST算法，该技术处于FOM 65.25 fJ的最新ADC之列/步。

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来源
《Circuits and systems》 |2015年第12期|280-291|共12页
作者
Ananthanarayanan Parthasarathy;
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作者单位

Department of Electrical Engineering, Stanford University, Stanford, USA;

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正文语种 eng
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关键词
Moving Binary Search Tree; SAR-ADC; Low Power;

机译：移动二进制搜索树;SAR ADC低电量;

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专利

1. An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS [J] . Ananthanarayanan Parthasarathy Circuits and Systems . 2015,第12期

机译：基于65 nm CMOS的8位0.8 GS / s 8.352 mW修改型基于逐次逼近寄存器的模数转换器
2. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration [J] . Liu W., Huang P., Chiu Y. Solid-State Circuits, IEEE Journal of . 2011,第11期

机译：具有数字校准功能的12位，45MS / s，3mW冗余逐次逼近寄存器模数转换器
3. A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS [J] . Yi Il-Min, Miura Naoki, Nosaka Hideyuki IEEE Journal of Solid-State Circuits . 2021,第2期

机译：基于4GS / s 11.3-MW 7位时间的ADC，具有折叠电压与时转换器和65-NM CMOS的流水线TDC
4. Performance verification of a 12-Bit, 25Msps, successive approximation register analogue-to-digital converter on 65nm CMOS [C] . Egan Maurice, MacNamee Ciaran, Scanlan Tony IET Irish Signals and Systems Conference . 2015

机译：在65nm CMOS上的12位，25Msps，逐次逼近寄存器模数转换器的性能验证
5. Successive-Approximation-Register Analog-to-Digital-Converter for Low-power CMOS Image Sensing and Compression [D] . Chen, Denis Guangyin. 2013

机译：逐次逼近寄存器模数转换器，用于低功耗CMOS图像感测和压缩
6. A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors [O] . Tao Lyu, Suying Yao, Kaiming Nie, 2014

机译：用于CMOS图像传感器的12位高速列并行两步单斜率模数转换器（ADC）
7. 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme [O] . Lei Sun, Chi Tung Ko, Marco Ho, 2014

机译：23μW8.9有效位数1.1 ms / s逐次逼近寄存器模数转换器，具有高能效的数模转换器切换方案

An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

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