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Optimization of Constant Matrix Multiplication with Low Power and High Throughput

机译：低功耗高吞吐量的恒定矩阵乘法的优化

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摘要

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where a single variable is multiplied by a constant vector. Like MCM, CMM can be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal number of add/subtract operations is known as the CMM problem. While this leads to a reduction in circuit area it may be less efficient for power consumption or throughput. It is well studied for the MCM problem that a) reducing the adder depth (AD) leads to a reduced power consumption and b) pipeline resources have to be considered during optimization to enhance throughput without wasting area. This paper addresses the optimization of CMM circuits which considers both adder depth and pipelining for the first time. For that, a heuristic is proposed which evaluates the most attractive graph topologies. It is shown that the proposed method requires 12.5% less adders with min. AD and 38.5% less pipelined operations. Synthesis results for recent FPGAs show that these reductions also translate to superior results in terms of delay and power consumption compared to the state-of-the-art.
机译：常数矩阵乘法（CMM），即常数矩阵与向量的乘法，是数字信号处理中的常见操作。它是多重常数乘法（MCM）的概括，其中单个变量乘以常数向量。像MCM一样，CMM可以减少到加/减和位移。寻找具有最少加/减运算次数的电路被称为CMM问题。虽然这会导致电路面积的减少，但对于功耗或吞吐量而言效率可能较低。对于MCM问题进行了充分的研究，其中a）减小加法器深度（AD）导致功耗降低； b）在优化过程中必须考虑管道资源以提高吞吐量而又不浪费面积。本文介绍了CMM电路的优化，它首次考虑了加法器深度和流水线技术。为此，提出了一种启发式算法，用于评估最具吸引力的图形拓扑。结果表明，所提出的方法最小需要加法器少12.5％。广告和流水线操作减少了38.5％。最新的FPGA的综合结果表明，与最新技术相比，这些减少还可以在延迟和功耗方面转化为出色的结果。

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