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首页> 外文期刊>ETRI journal >Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs
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Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs

机译：具有3D IC最小切割模分区的热感知布局

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Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.
机译：三维集成电路（3D IC）通过使用硅通孔（TSV）技术垂直堆叠几个平面芯片来在同一平台中实现异构系统。 3D IC具有一些优势，包括更短的互连长度，更高的集成密度和更高的性能。热感知设计将增强互连和设备的可靠性和性能。在本文中，我们提出了针对3D IC的最小切割管芯分区的热感知布局。提议的最小切割管芯分区方法基于最小切割定理，将分区之间的连接数量减到最少，并在将分区分配给模具时考虑两个分区之间连接的互补集，从而最小化TSV的数量。此外，热敏布局规划方法可确保在裸片中分配更均匀的功率并降低芯片的峰值温度。仿真结果表明，所提出的方法有效地减少了TSV的数量和峰值温度，同时还减少了运行时间。

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