Direct Digital Frequency Synthesizer Design and Implementation on FPGA

A.A. Alsharef; M.A. Mohd. Ali; H. Sanusi

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Direct Digital Frequency Synthesizer Design and Implementation on FPGA

机译：直接数字频率合成器的设计与FPGA实现

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This study presents a design and implementation of a direct digital frequency synthesizer based on Quarter Sine Wave. The RTL level simulation and gate level simulation of a proposed design is done by means of a Quartus-Model-Sim. This design is a digital part. The digital part consists of a Phase Accumulator (PA) and a Look up Table (LUT). The Phase Accumulator is implemented by means of a register along with an adder and feedback loop. LUT is implemented using verilog code. The size of LUT is reducing by storing quarter of sine wave in the ROM. This design was tested with various tuning frequencies and the result shows that the output frequency is directly proportional to the tuning input frequency.

机译：本研究提出了基于四分之一正弦波的直接数字频率合成器的设计和实现。拟议设计的RTL级仿真和门级仿真是通过Quartus-Model-Sim完成的。此设计是数字部分。数字部分包括一个相位累加器（PA）和一个查找表（LUT）。相位累加器通过寄存器以及加法器和反馈环路来实现。 LUT是使用Verilog代码实现的。通过将四分之一的正弦波存储在ROM中，LUT的尺寸得以减小。该设计在各种调谐频率下进行了测试，结果表明输出频率与调谐输入频率成正比。

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《Research Journal of Applied Sciences: RJAS》 |2012年第8期|共4页
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A.A. Alsharef; M.A. Mohd. Ali; H. Sanusi;
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Direct Digital Frequency Synthesizer Design and Implementation on FPGA

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