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首页> 外文期刊>Physical Review X >A Practical Phase Gate for Producing Bell Violations in Majorana Wires
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A Practical Phase Gate for Producing Bell Violations in Majorana Wires

机译：在马约拉纳群岛电线中产生钟声违规的实用相位门

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Carrying out fault-tolerant topological quantum computation using non-Abelian anyons (e.g., Majorana zero modes) is currently an important goal of worldwide experimental efforts. However, the Gottesman-Knill theorem [1] holds that if a system can only perform a certain subset of available quantum operations (i.e., operations from the Clifford group) in addition to the preparation and detection of qubit states in the computational basis, then that system is insufficient for universal quantum computation. Indeed, any measurement results in such a system could be reproduced within a local hidden variable theory, so there is no need for a quantum-mechanical explanation and therefore no possibility of quantum speedup [2]. Unfortunately, Clifford operations are precisely the ones available through braiding and measurement in systems supporting non-Abelian Majorana zero modes, which are otherwise an excellent candidate for topologically protected quantum computation. In order to move beyond the classically simulable subspace, an additional phase gate is required. This phase gate allows the system to violate the Bell-like Clauser-Horne-Shimony-Holt (CHSH) inequality that would constrain a local hidden variable theory. In this article, we introduce a new type of phase gate for the already-existing semiconductor-based Majorana wire systems and demonstrate how this phase gate may be benchmarked using CHSH measurements. We present an experimentally feasible schematic for such an experiment using a “measurement-only” approach that bypasses the need for explicit Majorana braiding. This approach may be scaled beyond the two-qubit system necessary for CHSH violations, leading to a well-defined platform for universal fault-tolerant quantum computation using Majorana zero modes.
机译：当前，使用非阿贝尔的任意子（例如，马约拉纳零模）进行容错拓扑量子计算是全球实验工作的重要目标。但是，Gottesman-Knill定理[1]认为，除了计算基础上的量子位状态的准备和检测之外，如果系统只能执行可用量子运算的某些子集（即，Clifford组的运算），则该系统不足以进行通用量子计算。实际上，这种系统中的任何测量结果都可以在局部隐藏变量理论中再现，因此不需要量子力学的解释，因此也没有量子加速的可能性[2]。不幸的是，Clifford运算恰好是在支持非阿贝尔马里亚纳零模的系统中通过编织和测量可获得的，否则，它们是拓扑受保护的量子计算的理想选择。为了超越经典的可模拟子空间，需要附加的相位门。此相位门使系统可以违反类似Bell的Clauser-Horne-Shimony-Holt（CHSH）不等式，后者会约束局部隐藏变量理论。在本文中，我们为已经存在的基于半导体的Majorana导线系统介绍了一种新型的相位门，并演示了如何使用CHSH测量对该相位门进行基准测试。我们提供了一种使用“仅测量”方法进行此类实验的实验上可行的示意图，该方法绕过了对明确的Majorana编织的需求。可以将这种方法扩展到超出违反CHSH所必需的两个量子位系统，从而为使用Majorana零模式的通用容错量子计算提供一个明确的平台。

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