A New Leakage Power Reduction Technique for CMOS VLSI Circuits

M. Geetha Priya; K. Baskaran; D. Krishnaveni; S. Srinivasan

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A New Leakage Power Reduction Technique for CMOS VLSI Circuits

机译：CMOS VLSI电路的降低泄漏功率的新技术

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A robust method which is equally effectual for static power control in CMOS VLSI circuits for System on Chip (Soc) applications in deep submicron technologies is proposed. Referring to the International Technology Roadmap for Semiconductors (ITRS), the total power dissipation may be significantly contributed by leakage power dissipation. To reduce leakage the proposed method introduces two self controlled stacked leakage control transistors (LT) between V_dd and ground, which offers high resistance, when it is in off state. The gate and substrate of each LT's are tied together to introduce Dynamic Threshold voltage MOSFET (DTMOS). This proposed method is intuitively momentous and leads to better performance measure in terms of dynamic power, leakage power propagation delay and Power Delay Product (PDP) with standard threshold devices. The experiment and simulation results show that the proposed method effectively outperforms than the base case with little area overhead.

机译：提出了一种健壮的方法，该方法对于深亚微米技术中的片上系统（Soc）应用的CMOS VLSI电路中的静态功率控制同样有效。参考国际半导体技术路线图（ITRS），总功耗可能由泄漏功耗引起。为了减少泄漏，所提出的方法在V _{dd 和地之间引入了两个自控堆叠泄漏控制晶体管（LT），当处于截止状态时，该晶体管提供高电阻。每个LT的栅极和衬底都绑在一起，以引入动态阈值电压MOSFET（DTMOS）。所提出的方法直观上很重要，并且可以通过标准阈值设备在动态功率，泄漏功率传播延迟和功率延迟乘积（PDP）方面实现更好的性能指标。实验和仿真结果表明，所提出的方法比基本情况具有更好的性能，且面积开销较小。}

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《Journal of Artificial Intelligence》 |2012年第4期|共页
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M. Geetha Priya; K. Baskaran; D. Krishnaveni; S. Srinivasan;
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A New Leakage Power Reduction Technique for CMOS VLSI Circuits

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