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Leakage Power Reduction by Adaptive Logic Cell technique in CMOS VLSI Digital circuit design

机译:CMOS VLSI数字电路设计中通过自适应逻辑单元技术降低泄漏功率

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摘要

Leakage power is becoming the major constraints in deep sub-micron technology. A new technique named as adaptive logic cell (ALC) is proposed that is adapted the logic cell which is in their Worst Leakage State (WLS) to further reduce the overall leakage power dissipation of the circuit. Once Minimum Leakage Vector (MLV) is achieved by using heuristic or exact algorithm for a given logic circuit, this approach is applied. It finds a logic cell which is in WLS and switches it with another cell having least leakage power dissipation with the same input vector. This is extension of IVC technique in which the cell in WLS is replaced and also it controls the intermediate gate while IVC is responsible only for primary input of the circuit. This new approach of ALC in WLS is valid when the logic depth is large otherwise IVC technique is appropriate for reducing the leakage power. The proposed technique is process independent and also no extra power supply is required. Proposed technique is simulated for NAND, NOR, EX-OR, EX-NOR, Half adder and Full adder using HSPICE simulator and achieves 72.56%, reduction of leakage while IVC reduce only 47.07%.
机译:泄漏功率正在成为深亚微米技术的主要限制。提出了一种称为自适应逻辑单元(ALC)的新技术,该技术适用于处于最坏泄漏状态(WLS)的逻辑单元,以进一步降低电路的总体泄漏功耗。一旦通过对给定逻辑电路使用启发式或精确算法来实现最小泄漏矢量(MLV),便可以采用这种方法。它找到一个位于WLS中的逻辑单元,并使用相同的输入矢量将其切换为泄漏功耗最小的另一个单元。这是IVC技术的扩展,其中替换了WLS中的单元,并且它控制中间门,而IVC仅负责电路的主要输入。当逻辑深度较大时,这种在WLS中使用ALC的新方法是有效的,否则IVC技术适合降低泄漏功率。所提出的技术与过程无关,并且不需要额外的电源。使用HSPICE模拟器对NAND,NOR,EX-OR,EX-NOR,EX-NOR,半加法器和全加法器进行了仿真,可达到72.56%,减少了泄漏,而IVC仅减少了47.07%。

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