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首页> 外文期刊>Journal of Low Power Electronics and Applications >Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology
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Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology

机译：多阈值NULL约定逻辑（MTNCL）：超低功耗异步电路设计方法

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This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster.
机译：本文开发了一种超低功耗异步电路设计方法，称为多阈值NULL约定逻辑（MTNCL），也称为睡眠约定逻辑（SCL），该方法将多阈值CMOS（MTCMOS）与NULL约定逻辑（NCL）结合在一起，以显着降低功耗，而没有将MTCMOS应用于同步电路的任何缺点。与通常导致大面积开销的其他功耗降低技术相比，MTNCL电路实际上比其原始NCL版本小。 MTNCL利用高V t 晶体管来控制低V t 逻辑块的电源和地，以在空闲时提供快速切换和极低的泄漏功率。为了证明MTNCL的优势，设计了许多32位IEEE单精度浮点协处理器，以使用1.2 V IBM 8RF-LM 130 nm CMOS工艺进行比较：原始NCL，仅带有组合逻辑的MTNCL（C / L）睡眠，Bit-Wise MTNCL（BWMTNCL），具有C / L和完成逻辑睡眠的MTNCL，具有C / L，完成逻辑和寄存器睡眠的睡眠，具有安全睡眠架构的MTNCL和同步MTCMOS。对这些设计进行了吞吐量，面积，动态能量和空闲功率方面的比较，显示了各种MTNCL架构之间的折衷，并且最佳的MTNCL设计在各个方面都比原始NCL设计要好得多，并且比原始NCL设计要好得多。尽管同步设计可以更快地运行，但从面积，每次操作的能量和空闲功率方面来说，同步MTCMOS设计还是可以的。

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