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首页> 外文期刊>Indian Journal of Science and Technology >A FPGA Implementation of Dual Images based Reversible Data Hiding Technique using LSB Matching with Pipelining
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A FPGA Implementation of Dual Images based Reversible Data Hiding Technique using LSB Matching with Pipelining

机译：使用流水线LSB匹配的基于双图像的可逆数据隐藏技术的FPGA实现

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Background: In this digital era, the authentication and proof of ownership has become a vital part in all the multimedia data content like audio, image and video. Data Hiding is one of the familiar methodologies used to authenticate and resolve the issues of copyrights of the digital data. Methods: In this paper the FPGA (Field Programmable Gate Array) implementation of Data Hiding using reversible Dual Image concept is carried out on a gray scale image. Here the FPGA implementation is carried out with and without the concept of pipelining. Findings: In the data hiding process the secret key is embedded in the host image content and analyzed with the values of PSNR (Peak Signal to Noise Ratio) and Embedding capacity. In the last, a comparison for the pipelined and non pipelined mode of data hiding process has been done for the values of area, power and timing. From the results it is noted that the pipelined mode of data hiding gives better result in terms of very less embedding time compared to non pipelined mode with a lesser power consumption. As this data hiding methodology involves only simple operation it is easy to implement as FPGA chip using Verilog HDL Modelling language. Here the entire data hiding operation is carried out by the hardware chip, not by software running on hardware, hence the process of data hiding is fast when compared with all other software implementations. As the whole process of embedding is taking place in real time, we can embed this FPGA data hiding chip as a separate co-processor the data hiding operation with any multimedia device.
机译：背景：在这个数字时代，身份验证和所有权证明已成为所有多媒体数据内容（如音频，图像和视频）中至关重要的部分。数据隐藏是用于认证和解决数字数据版权问题的一种熟悉的方法。方法：在本文中，使用可逆双重图像概念的数据隐藏的FPGA（现场可编程门阵列）实现是在灰度图像上进行的。在这里，FPGA实现是在有或没有流水线概念的情况下执行的。发现：在数据隐藏过程中，密钥被嵌入到主机图像内容中，并使用PSNR（峰值信噪比）和嵌入容量的值进行分析。最后，针对面积，功率和时序的值，对数据隐藏过程的流水线模式和非流水线模式进行了比较。从结果可以看出，与非流水线模式相比，数据隐藏的流水线模式与非流水线模式相比，以更少的嵌入时间提供了更好的结果，并且功耗更低。由于这种数据隐藏方法仅涉及简单的操作，因此很容易使用Verilog HDL建模语言将其实现为FPGA芯片。这里，整个数据隐藏操作是由硬件芯片而不是由硬件上运行的软件执行的，因此，与所有其他软件实现相比，数据隐藏的过程很快。由于整个嵌入过程都是实时进行的，因此我们可以将该FPGA数据隐藏芯片作为与任何多媒体设备进行数据隐藏操作的独立协处理器进行嵌入。

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