Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

著录项

• 来源
  《The Journal of Engineering》 |2019年第21期|7424-7427|共4页
• 作者

  Wei Xin; Xie Yi Z.; Xie Yu; Chen He;

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• 作者单位

  Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China;

  Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China;

  Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China;

  Beijing Inst Technol Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China;

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• 收录信息
• 原文格式 PDF
• 正文语种 eng
• 中图分类
• 关键词

  field programmable gate arrays; fault tolerant computing; fast Fourier transforms; redundancy; radiation hardening (electronics); microprocessor chips; reconfiguration time; multipath delay feedback FFT controller; dynamic partial reconfiguration scheme; fault-tolerant FFT processor; field programmable gate array; logical resources; storage resources; dynamic partial reconfiguration technique; fast Fourier transform FFT processor; novel FPGA scrubbing framework; high-energy particles; triple modular redundancy scheme; DPR controller; blind scrubbing; Xilinx PRC IP; single event upset;

  机译：现场可编程门阵列;容错计算;快速傅里叶变换;冗余;辐射硬化（电子）;微处理器芯片;重新配置时间;多径延迟反馈FFT控制器;动态部分重新配置方案;容错的FFT处理器;现场可编程门阵列;逻辑资源;存储资源;动态部分重新配置技术;快速傅里叶变换FFT处理器;新型FPGA擦洗框架;高能粒子;三重模块化冗余方案;DPR控制器;盲擦洗;Xilinx PRC IP;单一事件不安;