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首页> 外文期刊>Journal of Computers >Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers
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Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance Reconfigurable Computers

机译：将浮点科学计算内核的设计启发式高性能可重构计算机

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—Because of the increasing need to develop efficient high-speed computational kernels, researchers have been looking at various acceleration technologies. One approach is to use field programmable gate arrays (FPGAs) in conjunction with general purpose processors to form what are known as high performance reconfigurable computers (HPRCs). HPRCs have already been shown to work well for both fixed-point and integer calculations. Floating-point calculations are a different matter; obtaining speedups has been somewhat elusive. This article, after introducing the three primary HPRC development flows, takes a detailed look at “the three p’s,” which addresses the crucial relationship among performance, pipelining, and parallelism. It also examines “the FPGA design boundary,” which addresses some of the heuristics that allow developers to determine which application modules can be mapped onto the FPGAs. These ideas are illustrated by way of a simple floating-point application that is mapped onto a contemporary HPRC. This article expands upon earlier work by including details on how to map customized intellectual property cores into an HPRC environment via a hybrid development flow.
机译：- 因为越来越需要开发高效的高速计算内核，研究人员一直在寻找各种加速技术。一种方法是与通用处理器结合使用现场可编程门阵列（FPGA）以形成所谓的高性能可重新配置计算机（HPRC）。 HPRC已被证明适用于固定点和整数计算。浮点计算是一个不同的物质;获得加速已经难以捉摸。本文在介绍了三个主要的HPRC开发流程之后，请详细了解“三个P”，这解决了性能，流水线和并行性之间的关键关系。它还检查了“FPGA设计边界”，它解决了一些启发式方法，允许开发人员确定可以将哪些应用程序模块映射到FPGA上。这些想法是通过映射到当代HPRC的简单浮点应用程序来说明。本文通过包括如何通过混合开发流程将定制的知识产权核心映射到HPRC环境中的详细信息，扩展了早期的工作。

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