Students enrolled in a capstone design course on analog integrated circuits often encounter calculational difficulties when they attempt to verify key circuit parameters predicted by computer simulations using SPICE. Discrepancies between their hand calculations and SPICE values sometimes exceed 200%. This paper reviews some commonly encountered discrepancies, describes major causes of significant errors, and offers solutions that have been found to be effective. In particular, this paper discusses the impacts of variable transistor current gains (/spl beta//sub ac/ and /spl beta//sub dc/) on AC gain, input impedance, and quiescent point (Q point) determination. Since realistic computer simulations depend on realistic numerical models of active devices, SPICE parameters that realistically model BJTs, JFETs, and MOSFETs are given. The paper also discusses the large discrepancies typically found when calculating the output resistance (R/sub out/) of a Class AB push-pull stage operating near 0 VDC, the common mode rejection ratio (CMRR) of an actively loaded differential stage, and the frequency response of an internally compensated op amp circuit. Lastly, suggestions and recommendations for avoiding many calculational pitfalls also are presented.
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机译：参加模拟集成电路顶峰设计课程的学生在尝试验证使用SPICE进行的计算机仿真预测的关键电路参数时，经常会遇到计算困难。他们的手工计算与SPICE值之间的差异有时会超过200％。本文回顾了一些常见的差异，描述了重大错误的主要原因，并提供了已发现有效的解决方案。特别是，本文讨论了可变晶体管电流增益（/ spl beta // sub ac /和/ spl beta // sub dc /）对交流增益，输入阻抗和静态点（Q点）确定的影响。由于实际的计算机模拟取决于有源器件的实际数值模型，因此提供了对BJT，JFET和MOSFET进行实际建模的SPICE参数。本文还讨论了在计算在0 VDC附近工作的AB类推挽级的输出电阻（R / sub out /），有功负载的差分级的共模抑制比（CMRR）和内部补偿运算放大器电路的频率响应。最后，还提出了避免许多计算陷阱的建议。
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