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首页> 外文期刊>IEEE Transactions on Electron Devices >Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs
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Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

机译：深亚微米SOI N-MOSFET处于断态工作时的热载流子效应和寿命预测

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摘要

Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original V/sub t/ variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low V/sub d/ range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high V/sub d/, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability.
机译：在较深的亚微米N沟道SOI MOSFET中，在很宽的温度和栅极长度范围内，都对寄生双极晶体管（PBT）动作引起的热载流子效应（HCE）进行了深入研究。在所有实验条件下，器件的多级降级都得到了强调。对于短沟道器件，也可以获得原始的V / sub t /变化，在高应力漏极偏置的情况下，对于应力时间的中间值，可以观察到阈值电压的降低。在低温（LT）下，由于PBT方案中的泄漏电流显着降低，因此可以在低V / sub d /范围内获得器件老化的改善。然而，在高V / sub d /的情况下，由于在LT下不能抑制强泄漏电流，因此器件老化比在室温下获得的器件老化大。另一方面，在关断状态下的器件寿命是通过各种方法根据栅极长度进行仔细预测的。为了提出优化的绝缘体上硅（SOI）架构，还可以使用数值模拟来减轻PBT行为并改善器件性能和可靠性。

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