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Monte Carlo studies of hot-carrier degradation and device performance in low-power, deep submicron n-MOSFETs.

机译：蒙特卡洛研究了低功率深亚微米n-MOSFET中的热载流子退化和器件性能。

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摘要

In this thesis, hot-electron induced device degradation and device performance in silicon n-MOSFET's is studied theoretically. To accomplish this goal, we employ an ensemble Monte Carlo simulator that is adapted to model hot-carrier transport under low-voltage bias. The Monte Carlo model uses a realistic silicon band structure for the two lowest conduction bands, and contains all relevant aspects of 3-D electron transport including interactions with other 3-D electrons, acoustic and intervalley phonons, and ionized impurities along with impact ionization and interface scattering. Further, this Monte Carlo simulator is modified to model gate polysilicon depletion and channel carrier quantization.; The study is first applied to investigate scaling and device performance trends in channel engineered n-MOSFET's. The ensemble Monte Carlo device simulator is used to extract hot-carrier reliability and device performance for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800–100 nm. In the next part of the thesis, we employ a comprehensive Monte Carlo-based simulation method to compare the hot-electron induced device degradation and transistor performance for two competing doublegate SOI designs (one with a lightly-doped channel and one with a heavily-doped channel) and a comparable single-gate design. All three SOI devices have an effective channel length of 80 nm. The results of these investigations reveal that the location and strength of peak hot-electron injection is a strong function of internal device configurations. Together, measures of performance and hot-carrier degradation indicate that otherwise well-designed n-MOSFET's need careful evaluation as candidates for future device technologies.; Next, this work validates the new features of the Monte Carlo simulator including quantized channel carriers and polysilicon depletion through capacitance modeling. Overall, calculated and measured values of capacitance show good agreement, indicating that the quantization models coupled to a Poisson solution that accounts for polysilicon depletion performs reasonably well. To demonstrate the predictive capability of the channel quantization and polysilicon depletion models, the Monte Carlo simulator is used to evaluate a bulk n-channel MOSFET with an effective channel length of 25 nm. The predicted drain current from our Monte Carlo simulator compares well against drain current estimations from established simulation tools. Further, the Monte Carlo tool is used to examine occupation of the subbands by 2-D electrons in the 25 nm device. The mechanisms affecting subband occupation in highly nonuniform channel configurations have not been previously well documented. Simulation results suggest that the subband populations are highly influenced by 2-D carrier scattering near the source end of the channel and by quasi-ballistic transport near the drain side of the channel.
机译：本文从理论上研究了热电子诱导的硅n-MOSFET器件的性能退化和性能。为了实现此目标，我们采用了集成的蒙特卡洛模拟器，该模拟器适用于在低压偏置下对热载流子传输进行建模。蒙特卡洛模型对两个最低的导带使用了逼真的硅带结构，并包含了3D电子传输的所有相关方面，包括与其他3D电子，声子和音素，声子，电离杂质以及碰撞电离和界面散射。此外，修改了该蒙特卡罗仿真器以对栅极多晶硅损耗和沟道载流子量化进行建模。该研究首先应用于调查通道工程n-MOSFET的缩放和器件性能趋势。集成的蒙特卡洛器件仿真器用于提取超载流子退热和更常规的硅n-MOS设计的热载流子可靠性和器件性能，有效通道长度范围为800–100 nm。在本文的下一部分，我们采用一种基于Monte Carlo的综合仿真方法来比较两种竞争的双栅极SOI设计（一种具有轻掺杂沟道，另一种具有高掺杂沟道）的热电子感应器件的退化和晶体管性能。掺杂通道）和可比的单门设计。所有三个SOI器件的有效通道长度均为80 nm。这些研究的结果表明，峰值热电子注入的位置和强度是内部器件配置的强大功能。总之，性能和热载流子退化的衡量指标表明，精心设计的n-MOSFET需要作为未来器件技术的候选者进行仔细评估。接下来，这项工作验证了蒙特卡洛仿真器的新功能，包括通过电容建模实现的量化通道载波和多晶硅耗尽。总体而言，电容的计算值和测量值显示出良好的一致性，表明与考虑多晶硅损耗的Poisson解决方案耦合的量化模型表现良好。为了证明沟道量化和多晶硅耗尽模型的预测能力，使用蒙特卡罗仿真器评估有效沟道长度为25 nm的体n沟道MOSFET。来自我们的蒙特卡洛仿真器的预测漏极电流与已建立的仿真工具的漏极电流估计值进行了很好的比较。此外，蒙特卡洛工具用于检查25 nm器件中二维电子对子带的占用。以前尚未充分记录过影响高度非均匀信道配置中子带占用的机制。仿真结果表明，子带总体受到信道源端附近的二维载波散射和信道漏极侧附近的准弹道传输的强烈影响。

著录项

  • 作者

    Williams, Stewart Clark.;

  • 作者单位

    North Carolina State University.;

  • 授予单位 North Carolina State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1999
  • 页码 99 p.
  • 总页数 99
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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