The architecture of image analysis system for implementing parallel digital image processor

PRZEMYSLAW BRYLSKI; MICHAL STRZELECKI

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The architecture of image analysis system for implementing parallel digital image processor

机译：实现并行数字图像处理器的图像分析系统架构

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摘要

W artykule opisano now? architektur? równoleg?ego, cyfrowego procesora obrazu, zdolnego do realizacji kilku zadań przetwarzania takich jak segmentacja, wykrywania kraw?dzi oraz usuwanie szumu. Architektura I modyfikacje algorytmu przedstawione w niniejszym dokumencie maj? na celu zmniejszenie obszaru uk?adu FPGA zajmowanego przez pojedynczy piksel, stanowi?cy podstawow? jednostk? przetwarzania obrazu. Proponowane modyfikacje zwi?kszaj? funkcjonalno?? ca?ego systemu, pozwalaj? na realizacj? ró?nych operacji przetwarzania obrazu bazuj?cych na metodzie rozrostu obszaru, jak równie? umo?liwiaj? komunikacj? si? z urz?dzeniem za pomoc? protoko?ów internetowych.%This article describes a new architecture for a parallel, digital image processor which performs several image processing tasks like segmentation, edge detection and noise removal. The architecture and algorithm modifications presented in this paper are aimed for reduction the FPGA area of a pixel, which represents basic image processing unit. The proposed modifications increase functionality of the entire system by enabling different image processing operations based on the region growing methods as well as the possibility of communication with device via Internet protocols.

机译：文章介绍了吗？建筑？一个并行的数字图像处理器，能够执行多种处理任务，例如分割，边缘检测和噪声去除。本文档中介绍的架构和算法修改具有减少单个像素占用的FPGA系统面积，这是基本单元？图像处理。拟议的修改增加功能??整个系统，允许在执行中基于面积增长方法的各种图像处理操作，以及允许通讯？姐姐与设备一起使用％本文介绍了一种并行数字图像处理器的新体系结构，该处理器执行多种图像处理任务，例如分割，边缘检测和噪声消除。本文提出的架构和算法修改旨在减少代表基本图像处理单元的像素的FPGA面积。所提出的修改通过基于区域增长方法实现不同的图像处理操作以及通过Internet协议与设备进行通信的可能性，增加了整个系统的功能。

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来源
《Elektronika》 |2010年第3期|p.90-93|共4页
作者
PRZEMYSLAW BRYLSKI; MICHAL STRZELECKI;
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作者单位

Technical University of Lodz, Institute of Electronics;

Technical University of Lodz, Institute of Electronics;

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原文格式 PDF
正文语种 eng
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关键词
segmentation; image processor; FPGA;

机译：分割;图像处理器现场可编程门阵列;

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The architecture of image analysis system for implementing parallel digital image processor

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