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首页> 外文期刊>Circuits and Systems I: Regular Papers, IEEE Transactions on >Selective State Retention Power Gating Based on Formal Verification
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Selective State Retention Power Gating Based on Formal Verification

机译：基于形式验证的选择性状态保持功率门控

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摘要

This work is aimed to reduce the area and power consumption in low-power VLSI design. A new selective approach for State Retention Power Gating (SRPG) based on Module Checking formal verification techniques is presented, and so-called Selective SRPG (SSRPG). The proposed approach is applied in order to minimize the number of retention flip flops required for state retention during sleep mode. The proposed technique automatically selects a reduced set of retention flip flops which include only the indispensable flip flops required for a proper state recovery using some unique criteria. The criteria are represented as a set of formal properties using propositional formulas to analyze the flip-flop's input equations. Those properties are expressed in temporal logic formalism, specifically, in Computation Tree Logic (CTL). The extraction of the essential retention flip flops is carried out using common formal verification techniques. This work suggests an efficient alternative to the conventional SRPG and PG techniques. The proposed approach has been applied to a practical design with about 3000 FFs. The results demonstrate a saving factor of about 80% comparing to SRPG and thus reducing area, static power consumption and synthesis tool convergence run time. This leads to significant potential area reduction of up to 10% of the total chip area and similar energy impact. Other few published related SSRPG techniques require either exhaustive simulations or impractical design representation, and are not aimed to classify a specific flip flop in a given physical design. To the best of our knowledge this is the first time common Formal Verification Tools are used for applying a Selective SRPG approach.
机译：这项工作旨在减少低功耗VLSI设计中的面积和功耗。提出了一种新的基于模块检查形式验证技术的状态保持功率门控（SRPG）选择性方法，即所谓的选择性SRPG（SSRPG）。应用所提出的方法是为了最小化在睡眠模式期间状态保持所需的保持触发器的数量。所提出的技术自动选择减少的一组保留触发器，这些保留触发器仅包括使用某些唯一准则进行适当状态恢复所需的必不可少的触发器。使用命题公式来分析触发器的输入方程，将标准表示为一组形式属性。这些属性用时间逻辑形式主义，特别是计算树逻辑（CTL）表示。基本保留触发器的提取是使用常见的形式验证技术进行的。这项工作提出了一种有效的替代传统SRPG和PG技术的方法。所提出的方法已应用于具有约3000 FF的实际设计中。结果表明，与SRPG相比，节省了大约80％的成本，从而减少了面积，减少了静态功耗并缩短了合成工具的收敛时间。这导致潜在的潜在面积减少多达芯片总面积的10％，并且产生了类似的能量影响。其他一些已发布的相关SSRPG技术需要详尽的仿真或不切实际的设计表示，并且不旨在对给定的物理设计中的特定触发器进行分类。据我们所知，这是首次使用通用的形式验证工具来应用选择性SRPG方法。

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