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首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters
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An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters

机译:低功耗硬件效率FIR滤波器的设计算法

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摘要

A novel algorithm for designing low-power and hardware-efficient linear-phase finite-impulse response (FIR) filters is presented. The algorithm finds filter coefficients with reduced number of signed-power-of-two (SPT) terms given the filter frequency response characteristics. The algorithm is a branch-and-bound-based algorithm that fixes a coefficient to a certain value. The value is determined by finding the boundary values of the coefficient using linear programming. Although the worst case run time of the algorithm is exponential, its capability to find appreciably good solutions in a reasonable amount of time makes it a desirable CAD tool for designing low-power and hardware-efficient filters. The superiority of the algorithm on existing methods in terms of SPT term count, design time, hardware complexity, and power performance is shown with several design examples. Up to 30% reduction in the number of SPT terms is achieved over unoptimized Remez coefficients, which is 20% better than compared optimization methods. The average power saving is 20% over unoptimized coefficients, which is up to 14% better than optimized coefficients obtained with existing methods.
机译:提出了一种设计低功耗,硬件效率高的线性相位有限冲激响应(FIR)滤波器的新算法。在给定滤波器频率响应特性的情况下,该算法查找具有减少的二阶有符号功率(SPT)项数量的滤波器系数。该算法是基于分支定界的算法,可将系数固定为某个值。该值通过使用线性编程找到系数的边界值来确定。尽管该算法的最坏情况运行时间是指数级的,但其能够在合理的时间内找到相当好的解决方案的能力使其成为设计低功耗和硬件效率高的滤波器的理想CAD工具。通过几个设计示例,可以看出该算法在SPT项数,设计时间,硬件复杂性和电源性能方面在现有方法上的优越性。与未优化的Remez系数相比,SPT项数最多可减少30%,比比较优化方法好20%。与未优化的系数相比,平均功耗可节省20%,比通过现有方法获得的优化系数高14%。

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