Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Khandelwal Sourabh; Agarwal Harshit; Duarte Juan Pablo; Chan Kaiman; Dey Sagnik; Chauhan Yogesh Singh; Hu Chenming

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Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

机译：建模STI边缘寄生电流以进行精确的电路仿真

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摘要

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current at the shallow trench isolation edge. Accurate, efficient, and scalable model for is developed by finding the key differences between and main device drain current (). It is found that has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

机译：我们增强了行业标准紧凑模型BSIM6的能力，可以对浅沟槽隔离边缘处的寄生电流进行建模。通过找到主器件漏极电流与主器件漏极电流（）之间的关键差异，可以开发出一种精确，高效且可扩展的模型。与相比，发现具有不同的亚阈值斜率，体偏置系数和短通道行为。这些重要影响以及它们对器件几何形状，偏置条件和温度的依赖性都在模型中得到了说明。该模型与实验数据非常吻合，验证了其可扩展性和为生产水平使用做好准备。

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来源
《Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on》 |2015年第8期|1291-1294|共4页
作者
Khandelwal Sourabh; Agarwal Harshit; Duarte Juan Pablo; Chan Kaiman; Dey Sagnik; Chauhan Yogesh Singh; Hu Chenming;
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作者单位

Department of Electrical Engineering and Computer Science, University of California, Berkeley, Berkeley, CA, USA;

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原文格式 PDF
正文语种 eng
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关键词
Analog technology; BSIM6; Compact Models; Parasitic Currents; STI Edge Effects; compact models; parasitic currents; shallow trench isolation (STI) edge effects;

机译：模拟技术;BSIM6;紧凑模型;寄生电流;STI边缘效应;紧凑模型;寄生电流;浅沟槽隔离（STI）边缘效应;

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专利

1. Modeling MOS snapback and parasitic bipolar action forcircuit-level ESD and high-current simulations [J] . Amerasekera A., Mi-Chang Chang, Duvvury C., IEEE Circuits & Devices . 1997,第2期

机译：为电路级ESD和大电流仿真建模MOS骤回和寄生双极性作用
2. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations [J] . Amerasekera A., Mi-Chang Chang IEEE Circuits & Devices . 1997,第2期

机译：为电路级ESD和大电流仿真建模MOS骤回和寄生双极性作用
3. SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings [J] . Zhao Li, Shi C.-J.R. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第6期

机译：SILCA：具有SPICE精确度的迭代线性中心分析，可有效地对具有强寄生耦合的VLSI电路进行时域仿真
4. Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations [C] . Amerasekera A., Ramaswamy S., Mi-Chang Chang, Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International . 1996

机译：为电路级ESD和高电流仿真建模MOS骤回和寄生双极性作用
5. SPICE-accurate iterative methods for efficient time-domain simulation of VLSI circuits with strong parasitic couplings. [D] . Li, Zhao. 2005

机译：具有强大寄生耦合的VICE电路的高效时域仿真的SPICE精确迭代方法。
6. Hierarchical Stochastic Simulation Algorithm for SBML Models of Genetic Circuits [O] . Leandro H. Watanabe, Chris J. Myers 2014

机译：遗传电路的SBML模型的分层随机仿真算法
7. Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling [O] . Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 2013

机译：基于紧凑电流建模精确估算缩放CmOs逻辑电路中的总漏电流
8. Accurate Timing Model for Fault Simulation in MOS Circuits. [R] . Kim, S. 1989

机译：mOs电路故障仿真的精确定时模型。

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

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