...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >TAO-BIST: A framework for testability analysis and optimization for built-in self-test of RTL circuits
【24h】

TAO-BIST: A framework for testability analysis and optimization for built-in self-test of RTL circuits

机译：TAO-BIST：RTL电路内置自检的可测试性分析和优化框架

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (<99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0% and 1.5%, respectively, for a bit-width of 16. These overheads decrease further with an increase in bit-width. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low.
机译：在本文中，我们介绍了TAO-BIST，这是一个使用内置自测（BIST）测试寄存器传输级别（RTL）控制器-数据路径电路的框架。 RTL上的常规BIST技术通常引入比需要的硬件更多的可测试性硬件，从而导致不必要的面积，延迟和功耗。它们通常仅应用于专用集成电路（ASIC）。 TAO-BIST采用三阶段方法在RTL提供有效的BIST框架。在第一阶段，我们确定给测试电路添加一组初始的测试增强功能。在第二阶段，我们使用电路的BIST模型的基于正则表达式的高级符号可测试性分析，以完全封装被测模块的对正/传播信息。如此获得的正则表达式然后用于在最后阶段构造布尔函数，以确定满足延迟约束且面积开销最小的测试增强解决方案。我们的方法适用于各种电路，包括ASIC，专用可编程处理器（ASPP），专用指令处理器（ASIP），数字信号处理器（DSP）和微处理器。在多个基准电路上的实验结果表明，使用我们的方案可以获得较高的故障覆盖率（<99％）。对于16位宽，由于TAO-BIST引起的平均面积和延迟开销分别仅为6.0％和1.5％。这些开销随着位宽的增加而进一步降低。实现整个控制器-数据路径电路的高故障覆盖率的测试应用时间也很短。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号