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首页> 外文期刊>Dependable and Secure Computing, IEEE Transactions on >Modeling and Mitigating Transient Errors in Logic Circuits
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Modeling and Mitigating Transient Errors in Logic Circuits

机译：建模和缓解逻辑电路中的瞬态误差

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摘要

Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits.
机译：由各种环境影响引起的瞬态或软错误在微电子和纳米电子学中日益引起关注。我们提供了一个通用框架，用于建模和减轻数字电路中此类错误的逻辑影响。我们观察到一些错误会产生时间限制。系统的输出在几个时钟周期内被破坏，然后它会自动恢复。由于某些应用程序可以容忍这种错误行为，即在系统级别上这不是关键问题，因此我们将关键软错误率（CSER）定义为常规SER度量的更实际替代方案。提出了一种简化的，与技术无关的故障模型，即单一瞬态故障（STF），用于有效地估计组合逻辑和顺序逻辑中与各个节点相关的错误概率。 STF可以用于计算感兴趣的故障和错误的各种其他有用指标，并且所需的计算可以利用为（永久）滞留故障而设计的大量现有方法和工具。作为所提出方法的一种应用，我们介绍了一种针对瞬态故障强化逻辑电路的系统策略。目标是通过选择用于增强STF的节点子集，以最低的成本实现所需的CSER水平。提出了解决节点选择问题的精确算法和近似算法。通过使用ISCAS-85和-89基准套件以及一些大型（数百万门）工业电路的实验证明了这种方法的有效性。

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