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Environmental effects in component packaging selection

机译：组件包装选择中的环境影响

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Design for environment activities in electronics have been focused on issues of product life-cycle at the board design level and to facility-level process and material choices at the semiconductor fabrication level. An important bridge between these two domains has been the influence of component selection, particularly packaging selection, on environmental impacts. Component packaging influences waste generation in two respects. First, packaging type (i.e. DIP, QFP, BGA, etc.) and size dictates direct production waste in stamping, molding and plating operations. The waste streams from these operations include copper, polymerized thermoset plastic, caustic and acidic effluents and also small traces of silver epoxy. Since many waste components are nonrecyclable and/or have high hazardous content, effective management of direct waste emissions is a critical design task. Second, packaging selection indirectly affects waste generation at the printed circuit board (PCB) level through layout and board sizing decisions. The waste streams from board fabrication include composite scrap (usually glass epoxy), metals (copper foil and dissolved solutions) and catalyst wastes (aqueous photoresist, developer and stripper solutions and hole drilling scrap and tooling). The analysis approach undertaken in this study relies on the development of a toolset of unit process models for packaging manufacturing which develops relationships between package parameters, process parameters and waste outputs. By linking a chain of process models, a mathematical description of a packaging production sequence can be estimated. The models are formulated using the line data collected on plastic quad flat package (PQFP) lines. From the process models, a case comparison of the environmental impacts for two alternative packages for components is developed. Two designs, a design that employs almost all small outline integrated circuits (SOICs) and dual in-line packages (DIPs) (except where lead count necessitates PQFPs) vs. the same design that employs all PQFPs are considered. A case study illustrating the corresponding PCB level impacts due to component packaging selection is also presented. The bare board chosen in both cases is a standard FR4 board.
机译：电子产品中的环境活动设计一直侧重于板设计级的产品生命周期问题，以及半导体制造级的设施级工艺和材料选择。这两个领域之间的重要桥梁是组件选择（尤其是包装选择）对环境影响的影响。组件包装从两个方面影响废物的产生。首先，包装类型（即DIP，QFP，BGA等）和尺寸决定了冲压，成型和电镀操作中的直接生产浪费。这些操作产生的废物流包括铜，聚合的热固性塑料，腐蚀性和酸性流出物以及少量的环氧银。由于许多废物成分不可回收和/或具有很高的危险含量，因此有效管理直接废物排放是一项关键的设计任务。其次，包装的选择会通过布局和电路板尺寸决定间接影响印刷电路板（PCB）级别的废物产生。电路板制造产生的废物流包括复合废料（通常是玻璃环氧树脂），金属（铜箔和溶解的溶液）和催化剂废物（光致抗蚀剂水溶液，显影剂和剥离剂溶液以及钻孔废料和工具）。在这项研究中进行的分析方法依赖于包装生产的单位过程模型工具集的开发，该工具集开发了包装参数，过程参数和废物输出之间的关系。通过链接过程模型链，可以估算包装生产顺序的数学描述。这些模型是使用在塑料四方扁平包装（PQFP）线上收集的线数据制定的。从过程模型中，开发了两个替代组件包装对环境影响的案例比较。考虑到两种设计，即采用几乎所有小型集成电路（SOIC）和双列直插式封装（DIP）的设计（除非引线数需要PQFP的情况）与采用所有PQFP的相同设计。还提供了一个案例研究，说明了由于组件封装选择而引起的相应PCB等级影响。两种情况下选择的裸板都是标准的FR4板。

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