Majority Logic Decoding Under Data-Dependent Logic Gate Failures

Srdan Brkic; Predrag Ivaniš; Bane Vasić

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Majority Logic Decoding Under Data-Dependent Logic Gate Failures

机译：数据相关逻辑门故障下的多数逻辑解码

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摘要

A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.

机译：分析了由不可靠逻辑门构成的多数逻辑解码器，其故障是瞬态的并且与数据有关。基于故障配置的组合表示，针对常规低密度奇偶校验（LDPC）代码集合和所提出的故障模型，得出了单步多数逻辑解码器的平均误码率的闭式表达式。然后，在简化的概率门输出切换模型下，使用提出的分析框架建立单步多数逻辑解码器性能的界限。基于LDPC码的Tanner图的扩展特性，证明了一种错误的并行位翻转解码器版本可以在存在依赖于数据的门故障的情况下纠正固定比例的通道错误。结果用有限几何代码的数字示例说明。

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来源
《IEEE Transactions on Information Theory》 |2017年第10期|6295-6306|共12页
作者
Srdan Brkic; Predrag Ivaniš; Bane Vasić;
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作者单位

School of Electrical Engineering, University of Belgrade, Belgrade, Serbia;

School of Electrical Engineering, University of Belgrade, Belgrade, Serbia;

Department of Electrical and Computer Engineering, The University of Arizona, Tucson, AZ, USA;

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正文语种 eng
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关键词
Decoding; Logic gates; Circuit faults; Noise measurement; Iterative decoding; Reliability;

机译：解码;逻辑门;电路故障;噪声测量;迭代解码;可靠性;

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机译：CMOS多数逻辑门及其在单步ML可解码代码中的应用
2. Performance analysis of a two-step decoding method based on majority logic decoding and ordered statistic decoding [J] . Jungjade Shiowattana, Toru Fujiwara 電子情報通信学会技術研究報告. ITS. Intelligent Transport Systems Technology . 2001,第732期

机译：基于多数逻辑解码和有序统计解码的两步解码方法的性能分析
3. Performance analysis of a two-step decoding method based on majority logic decoding and ordered statistic decoding [J] . Jungjade Shiowattana, Toru Fujiwara 電子情報通信学会技術研究報告. スペクトル拡散 . 2001,第730期

机译：基于多数逻辑解码和有序统计解码的两步解码方法的性能分析
4. Analysis of one-step majority logic decoding under correlated data-dependent gate failures [C] . Brkic, Srdan, Ivanis, Predrag, Vasic, Bane Institute of Electrical and Electronics Engineers International Symposium on Information Theory . 2014

机译：相关数据相关门故障下的单步多数逻辑解码分析
5. Majority logic and majority spaces in contrast with ultrafilters. [D] . Salame, Samer. 2006

机译：与超滤器相比，多数逻辑和多数空间。
6. Implementation of cascade logic gates and majority logic gate on a simple and universal molecular platform [O] . Jinting Gao, Yaqing Liu, Xiaodong Lin, -1

机译：在简单通用的分子平台上实现级联逻辑门和多数逻辑门
7. Majority Logic Decoding under Data-Dependent Logic Gate Failures [O] . Brkic, Srdan, Ivanis, Predrag, Vasic, Bane 2015

机译：数据相关逻辑门故障下的多数逻辑解码
8. An Error-Control System Based on Majority-Logic Decoding. [R] . brown, r. b. chen, c. l. 1974

机译：一种基于多数逻辑解码的差错控制系统。

Majority Logic Decoding Under Data-Dependent Logic Gate Failures

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