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Majority voting circuit sensitive to at least three logic input signals, generating system clock signal, processes the majority vote.To generate a clock signal lead, and to test the majority vote of a number of input signals to logic, and,Device for testing the majority vote of a number of input signals;
Majority voting circuit sensitive to at least three logic input signals, generating system clock signal, processes the majority vote.To generate a clock signal lead, and to test the majority vote of a number of input signals to logic, and,Device for testing the majority vote of a number of input signals;
"The majority voting circuit sensitive to at least three logic input signals, generating system clock signal, processes the majority vote.To generate a clock signal lead, and to test the majority vote of a number of input signals to logic, and,Device for testing the majority vote of a number of input signals to logic ". The invention relates to a majority vote.A number of input signals are monitored individually by separate monitors, one monitor for each signal.Each monitor generates a control signal representing the state of the signal monitored. The control signals generated are sent to a control unit level.The control unit level controls the input levels to a "voter" majority according to the control signals.Instead of signs that are faulty, the control unit level selects signals being sent to the logic levels specific to the majority logic.The levels of these so-called logical replacement signals are selected such that the replacement signals do not interfere with the correct signals remaining.Further, the output signal of the majority vote is monitored so as to selectively generate an alarm.The functionality of the vote is tested by stopping input signals according to a first procedure, generating an alarm.Stopping input signals according to a second procedure, an alarm is avoided.
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