...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE transactions on nanotechnology >SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs
【24h】

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

机译：具有低RC延迟的SOI单电子晶体管，用于逻辑单元和SET / FET混合IC

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.
机译：我们报告成功制造出具有低RC时间常数的硅基单电子晶体管（SET）及其在互补逻辑单元和SET /场效应晶体管（FET）混合集成电路中的应用。通过与图案有关的氧化（PADOX）技术结合电子束光刻，在绝缘体上硅（SOI）结构上制造SET。在4.2 K下测得的漏极电导接近微西门子级的大值，表现出库仑振荡，峰谷电流比/ spl Gt / 1000。使用PADOX可能的机制进行数据分析时，其固有速度为/ spl sim / 2 THz，在理论量子极限的数量级内。将这些SET作为基本元素，在SOI芯片上制造了平面侧栅极控制的互补逻辑单元和SET / FET混合集成电路。这种面内结构在Si制造过程中非常有效，并且与电子岛相邻的侧栅极可以容易地控制库仑振荡的相位。逻辑单元的输入输出电压传输表现出反相行为，其中在4.2 K时输出电压增益估计约为1.2。由一个SET和三个FET组成的SET / FET混合集成电路产生了高具有宽范围输出窗口的电压增益和功率放大，以驱动下一个电路。最后，将30 mV的小SET输入栅极电压转换为400 mV，对应于13的放大率。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号