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首页> 外文期刊>Nuclear Science, IEEE Transactions on >Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation
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Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

机译:基于瞬态电离辐射的基于SRAM的FPGA中额外组合延迟的电路级建模

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摘要

This paper presents circuit level models that explain the extra combinational delays in a SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra combinational delays are simulated based on the circuit architecture of the FPGA core, namely Configurable Logic Blocks (CLBs) and routing. It is found that the main delay contribution originates from extra interconnection lines that are unintentionally connected to the main circuit path via pass transistors activated by SEUs. Moreover, longer delay faults observed on Input/Ouput Blocks (IOBs) due to SEU were investigated through simulations. In all cases, results are in close agreement with the ones obtained experimentally while exposing the FPGA to proton irradiation.
机译:本文介绍了电路级模型,这些模型解释了由于单事件翻转(SEU)而在基于SRAM的FPGA(Virtex-5)中产生的额外组合延迟。基于FPGA内核的电路架构,模拟了几种额外的组合延迟场景,即可配置逻辑块(CLB)和路由。可以发现,主要的延迟影响源于多余的互连线,这些互连线通过SEU激活的传输晶体管无意地连接到主电路路径。此外,通过仿真研究了由于SEU在输入/输出块(IOB)上观察到的更长的延迟故障。在所有情况下,结果都与将FPGA暴露于质子辐照下的实验结果非常吻合。

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