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首页> 外文期刊>IEEE Transactions on Nuclear Science >Single event upset test structures for digital CMOS application specific integrated circuits
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Single event upset test structures for digital CMOS application specific integrated circuits

机译：用于数字CMOS专用集成电路的单事件翻转测试结构

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摘要

A test structure methodology for digital CMOS ASICs (application-specific integrated circuits) that can be used to evaluate the hardness of various ASIC libraries and processes is described. The method identifies categories of ASIC cells and uses a select set of worst-case test structures to obtain the parameters necessary to evaluate a library and process, and make a tractable, bounded estimate of the expected chip hardness. In addition, if the error rates prove to be excessive, this method helps identify the cells in which hardening efforts will be most productive. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU (single event upset) response and designing a structure to characterize each response for each category. These methods are being applied in the development of ASIC options for hardened chip design and have already been used to design an SEU hardened ASIC controller.
机译：描述了一种可用于评估各种ASIC库和过程的硬度的数字CMOS ASIC（专用集成电路）的测试结构方法。该方法可识别ASIC单元的类别，并使用一组最坏情况的测试结构来获得评估库和工艺所需的参数，并对预期的芯片硬度做出易于处理的有界估计。另外，如果错误率证明过高，则此方法可帮助确定强化工作最有效的单元。该方法通过根据ASIC库单元的SEU（单事件翻转）响应进行分类并设计一种结构来表征每个类别的每个响应，从而将所需的测试结构的数量降至最低。这些方法已用于开发用于加固芯片设计的ASIC选项，并且已经用于设计SEU加固ASIC控制器。

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