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首页> 外文期刊>IEEE Transactions on Reliability >Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory
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Process Variation Aware Read Performance Improvement for LDPC-Based nand Flash Memory

机译：基于LDPC的nand闪存的过程差异感知读取性能提高

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摘要

With the rapid development of technology scaling and cell density improvement for capacity increase and cost reduction, nand flash memory is confronted with degraded reliability. On one hand, while low-density parity-check (LDPC) codes have been deployed in today's nand flash memories to enhance reliability, flash read latency has still been a performance bottleneck with the increased raw bit error rates (RBER). On the other hand, significant process variations (PV) have been found on existing nand flash memories, which introduce great reliability variations among different flash blocks. Recent studies have proposed to exploit PV to improve endurance by better wear leveling or to improve write performance. These approaches are prone to allocate read data to blocks with low reliability, which further degrades read performance. This paper proposes to enhance read performance of LDPC-equipped nand flash memory by exploiting the reliability variations from PV. The paper consists of three parts. First, a block grouping approach is presented to categorize flash blocks according to their reliability. Second, according to the grouping scheme, a data placement scheme is proposed, which allocates read-hot data to flash blocks with high reliability. At the same time, the read-cold data is moved to blocks with low reliability. As a result, the read performance is enhanced. However, allocating high reliable blocks for read-hot data collides with previous PV-based wear leveling methods. To address the issue, the third part is a grouping partition scheme which limits the amount of high reliable blocks occupied by read-hot data. Therefore, read performance enhancement can be achieved and the wear leveling schemes will be impacted slightly. Experiment results present that, the proposed approach can provide significant read performance improvement on LDPC-equipped nand flash memory and is compatible with the previous PV-based wear leveling.
机译：随着技术规模的迅速发展和单元容量的提高以提高容量和降低成本，nand闪存面临可靠性下降的问题。一方面，虽然低密度奇偶校验（LDPC）代码已被部署在当今的nand闪存中以提高可靠性，但闪存读取延迟仍然是原始误码率（RBER）增加的性能瓶颈。另一方面，在现有的nand闪存中发现了显着的工艺变化（PV），这在不同的闪存块之间引入了很大的可靠性变化。最近的研究提出利用PV来改善耐磨性或改善写入性能，从而提高耐用性。这些方法倾向于以低可靠性将读取数据分配给块，这进一步降低了读取性能。本文提出通过利用PV的可靠性差异来提高配备LDPC的nand闪存的读取性能。本文由三部分组成。首先，提出了一种块分组方法，以根据闪存块的可靠性对其进行分类。其次，根据分组方案，提出了一种数据放置方案，该方案以高可靠性将读取的热数据分配给闪存块。同时，读取的冷数据被移动到可靠性较低的块中。结果，增强了读取性能。但是，为读取热数据分配高可靠性块会与以前的基于PV的损耗均衡方法相冲突。为了解决该问题，第三部分是分组分区方案，该方案限制了读取热数据所占用的高可靠块的数量。因此，可以实现读取性能的增强，并且损耗平衡方案将受到轻微影响。实验结果表明，该方法可以在配备LDPC的nand闪存上显着提高读取性能，并且与以前基于PV的损耗均衡技术兼容。

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