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首页> 外文期刊>IEICE Transactions on Electronics >16 x 16 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks
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16 x 16 Two-Dimensional Optoelectronic Integrated Receiver Array for Highly Parallel Interprocessor Networks

机译：适用于高度并行处理器间网络的16 x 16二维光电集成接收器阵列

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摘要

A two-dimensional receiver OEIC array having an address selector for highly parallel interprocessor networks has been realized. The receiver OEIC array consists of two-dimensionally arranged 16x16(256) optical receiver cells with switching transistors, address selectors (decoders), and a comparator. Each optical receiver comprises a pin PD and a transimpedance-type HBT amplifier. The HBT has an InP passivation structure to suppress the emitter-size effect, which results in the improvement of current gains, especially at low collector current densities. The receiver OEIC array was fabricated on a 3-inch diameter InP substrate with pin/HBT integration technology. Due to the function of address selection, only one cell is activated and the other cells are mute, so the receiver OEIC array shows low crosstalk and low power consumption characteristics. The array also shows a 266-Mb/s data transmission capability. This receiver OEIC array is a most complex InP-based OEIC ever reported. The realization of the two-dimensional receiver OEIC array promises the future interprocessor networks with highly parallel optical interconnections.
机译：已经实现了具有用于高度并行处理器间网络的地址选择器的二维接收机OEIC阵列。接收器OEIC阵列由二维排列的16x16（256）光接收器单元组成，带有开关晶体管，地址选择器（解码器）和比较器。每个光接收器包括一个引脚PD和一个跨阻型HBT放大器。 HBT具有InP钝化结构以抑制发射极尺寸效应，从而导致电流增益的改善，尤其是在低集电极电流密度的情况下。接收器OEIC阵列是在采用pin / HBT集成技术的3英寸直径InP基板上制造的。由于地址选择功能，只有一个单元被激活，而其他单元则被静音，因此接收机OEIC阵列显示出低串扰和低功耗特性。该阵列还显示了266 Mb / s的数据传输能力。该接收器OEIC阵列是有史以来最复杂的基于InP的OEIC。二维接收器OEIC阵列的实现有望实现具有高度并行光互连的未来处理器间网络。

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