Evolutionary Graph Generation System with Terminal-Color Constraint-An Application to Multiple-Valued Logic Circuit Synthesis--

Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi

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Evolutionary Graph Generation System with Terminal-Color Constraint-An Application to Multiple-Valued Logic Circuit Synthesis--

机译：具有终端颜色约束的演化图生成系统在多值逻辑电路综合中的应用-

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This letter presents an efficient graph-based evolutionary optimization technique, and its application to the transistor-level design of multiple-valued arithmetic circuits. The key idea is to introduce "circuit graphs with colored terminals" for modeling heterogeneous networks of various components. The potential of the proposed approach is demonstrated through ex- perimental synthesis of a radix-4 signed-digit (SD) full adder cir- cuit.

机译：这封信提出了一种有效的基于图的进化优化技术，并将其应用于多值算术电路的晶体管级设计。关键思想是引入“带有彩色端子的电路图”，以对各种组件的异构网络进行建模。通过对基数为4的数字（SD）全加法器电路进行实验综合，证明了该方法的潜力。

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《IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences》 |2001年第11期|p.2808-2810|共3页
作者
Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi;
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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
multiple-valued logic; arithmetic circuits; evolution-;

机译：多值逻辑;运算电路;演化-;

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专利

1. Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design [J] . Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences . 2002,第9期

机译：具有终端颜色约束的并行进化图生成及其在电流模式逻辑电路设计中的应用
2. Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis [J] . MASANORI NATSUI, NAOFUMI HOMMA, TAKAFUMI AOKI, Journal of multiple-valued logic and soft computing . 2005,第5a6期

机译：基于图的进化综合设计多值逻辑电路
3. Self-checking multiple-valued integrated circuit based on dual-rail current-mode logic and its application to a high-performance arithmetic VLSI system [J] . Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama 電子情報通信学会技術研究報告. フォ-ルトトレラントシステム . 2000,第30期

机译：基于双轨电流模式逻辑的自检多值集成电路及其在高性能算术VLSI系统中的应用
4. Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis [C] . Natsui, M., Aoki, . 2002

机译：PC机群上的并行进化图生成及其在多值电路综合中的应用
5. Graphene nanotechnology for the next generation logic, memory, and 3D integrated circuits. [D] . Hossain, Md Nahid. 2016

机译：石墨烯纳米技术用于下一代逻辑，存储器和3D集成电路。
6. A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA [O] . Peer Zahoor Ahmad, S.M.K. Quadri, Firdous Ahmad, 2017

机译：一种使用QCA实现具有成本效益的算术逻辑电路的新型可逆逻辑门及其系统方法
7. Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits [O] . Kwang-Jow Gan, Jeng-Jong Lu, Wen-Kuan Yeh, 2016

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8. Multiple-Valued Logic System for Circuit Extraction to VHDL 1076-1987 [R] . Dukes, M. A. 1988

机译：用于VHDL 1076-1987电路提取的多值逻辑系统

Evolutionary Graph Generation System with Terminal-Color Constraint-An Application to Multiple-Valued Logic Circuit Synthesis--

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