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首页> 外文期刊>Image Processing, IET >Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation
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Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation

机译：多重提升计算的折叠二维离散小波变换的面积延迟功率高效架构

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摘要

Multiple lifting computation could be performed for block processing of two-dimensional (2D) discrete wavelet transform (DWT) by combined-lifting (CLF) or separated-lifting (SLF) approaches. CLF and SLF have the same computational complexities but they differ by their register requirements. In this study, the authors have chosen CLF for row processing and SLF for column processing, and suggested an efficient scheduling scheme for the computation of block-based lifting 2D DWT. Based on this approach, the authors have derived a parallel-pipeline structure for high-throughput implementation of one-level lifting 2D DWT. The authors have partitioned the multilevel 2D DWT computation appropriately and mapped that to a folded structure where the frame-buffer size is independent of input block size. The proposed structure requires 3N on-chip memory words, which is the lowest among all the existing similar structures. Compared with the best of the existing block-based structures for the one-level DWT, the proposed structure involves less on-chip memory words, requires the same number of multipliers and adders and offers the same throughput rate. The application specific integrated circuit (ASIC) synthesis result shows that the proposed structure involves significantly less area-delay-product and less energy per image than those of the best of the available designs.
机译：可以通过组合提升（CLF）或分离提升（SLF）方法对二维（2D）离散小波变换（DWT）的块处理执行多次提升计算。 CLF和SLF具有相同的计算复杂度，但是它们的寄存器要求不同。在这项研究中，作者选择CLF进行行处理，选择SLF进行列处理，并提出了一种有效的调度方案来计算基于块的提升2D DWT。基于这种方法，作者得出了一种并行流水线结构，用于高级别实现2D DWT的单层提升。作者已经适当地划分了多级2D DWT计算，并将其映射到折叠结构，其中帧缓冲区大小与输入块大小无关。所提出的结构需要3N的片上存储字，在所有现有的类似结构中最低。与用于一级DWT的现有基于块的最佳结构相比，该结构涉及更少的片上存储器字，需要相同数量的乘法器和加法器以及提供相同的吞吐率。专用集成电路（ASIC）的综合结果表明，与最佳设计相比，该结构所涉及的面积延迟积和每张图像的能量明显更少。

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  • 来源
    《Image Processing, IET》 |2014年第6期|345-353|共9页
  • 作者

    Mohanty B.K.; Meher P.K.;

  • 作者单位

    Electronics and Communication Engineering, Jaypee University of Engineering and Technology, Raghogarh, Madhya Pradesh, India|c|;

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