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Hardware design of LIF with Latency neuron model with memristive STDP synapses

机译：具有忆阻性STDP突触的潜伏神经元模型的LIF的硬件设计

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摘要

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks.
机译：本文提出了神经形态系统的硬件实现。该系统由具有潜伏期的渗漏集成和发射（LIFL）神经元和依赖于尖峰计时的可塑性（STDP）突触组成。与通常用于神经形态实现的通用集成即火模型相比，LIFL神经元模型可以编码更多信息。在我们的系统中，LIFL神经元使用CMOS电路实现，而忆阻器用于STDP突触的实现。提供了整个电路的描述。最后，通过模拟由三个神经元和两个突触组成的基序，评估了所提出体系结构的功能。仿真结果证实了该系统的有效性及其在设计更复杂的尖峰神经网络中的适用性。

著录项

  • 来源
    《Integration》 |2017年第9期|81-89|共9页
  • 作者

    Acciarito Simone; Cardarilli Gian Carlo; Cristini Alessandro; Di Nunzio Luca; Fazzolari Rocco; Khanal Gaurav Mani; Re Marco; Susi Gianluca;

  • 作者单位

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy;

    Univ Roma Tor Vergata, Dept Elect Engn, Via Politech 1, I-00133 Rome, Italy|Tech Univ Madrid, Ctr Biomed Technol, Lab Cognit & Computat Neurosci UCM UPM, Madrid, Spain;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Leaky Integrate-and-Fire with Latency (LIFL); Neuron; Synapse; STDP; Memristor; Neuromorphic system; Analog VLSI;

    机译：漏电时延集成与发射（LIFL）;Neuron;Synapse;STDP;忆阻器;神经形态系统;模拟VLSI;

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