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A 12-bit 4928 x 3264 pixel CMOS image signal processor for digital still cameras

机译：用于数码相机的12位4928 x 3264像素CMOS图像信号处理器

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摘要

In this paper a 4928 x 3264 pixel CMOS image signal processor (ISP) is proposed for digital still cameras with low complexity and high performance. To reduce hardware cost and keep high performance, novel algorithms are proposed to process image signals. Firstly, a joint demosaic and denoise algorithm is presented for both color interpolation and Gaussian noise removal. This novel joint algorithm achieves high performance and saves line buffers. Furthermore, image edge enhancement is performed jointly with this algorithm to save memory cost. Secondly, a low complexity auto white balance hardware architecture is presented based on histogram equalization algorithm. This algorithm can handle some extremely bad scenes. To reduce hardware cost, the contrast enhancement is realized jointly with auto white balance. Thirdly, to remove pulse noise, a high performance and low complexity hardware implementation is proposed based on median filter using only nine comparators. Based on these algorithms and hardware, the VLSI architecture of the ISP is proposed and implemented in a SMIC 65 nm CMOS technology. The gate count of the ISP is 158k and core area is 1.5 mm(2). Only 8 line buffers with total 462 Kb SRAM are used in the ISP. The throughput of the ISP is 12 Gb/s with a frequency of 333 MHz and power consumption of 77 mW.
机译：本文提出了一种4928 x 3264像素CMOS图像信号处理器（ISP），用于低复杂度和高性能的数码相机。为了降低硬件成本并保持高性能，提出了新颖的算法来处理图像信号。首先，提出了一种去马赛克和去噪联合算法，用于颜色插值和高斯噪声去除。这种新颖的联合算法可实现高性能并节省行缓冲区。此外，与该算法一起执行图像边缘增强以节省存储成本。其次，提出了一种基于直方图均衡算法的低复杂度自动白平衡硬件架构。该算法可以处理一些极其恶劣的场景。为了降低硬件成本，对比度增强与自动白平衡一起实现。第三，为了消除脉冲噪声，基于仅使用九个比较器的中值滤波器，提出了一种高性能和低复杂度的硬件实现。基于这些算法和硬件，提出并在SMIC 65 nm CMOS技术中实现了ISP的VLSI架构。 ISP的门数为158k，核心区域为1.5 mm（2）。 ISP中仅使用8个总462 Kb SRAM的行缓冲器。 ISP的吞吐量为12 Gb / s，频率为333 MHz，功耗为77 mW。

著录项

  • 来源
    《Integration》 |2017年第9期|206-217|共12页
  • 作者

    Jin Wei; He Guanghui; He Weifeng; Mao Zhigang;

  • 作者单位

    Shanghai Jiao Tong Univ, Circuits & Syst, Shanghai, Peoples R China;

    Shanghai Jiao Tong Univ, Shanghai, Peoples R China;

    Shanghai Jiao Tong Univ, Dept Micronano Elect, Shanghai, Peoples R China;

    Shanghai Jiao Tong Univ, Shanghai, Peoples R China|Shanghai Jiao Tong Univ, Dept Micronano Elect, Shanghai, Peoples R China;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Bayer image format; Digital still camera (DSC); Image signal processor (ISP); VLSI implementation;

    机译：拜耳图像格式;数码相机（DSC）;图像信号处理器（ISP）;VLSI实现;

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