A design example of a 65 nm CMOS operational amplifier

Franz Schloegl; Horst Zimmermann

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A design example of a 65 nm CMOS operational amplifier

机译：65 nm CMOS运算放大器的设计实例

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摘要

In this paper, we discuss the properties of new nanometer-size CMOS technologies being important for the circuit designer. Thereby we concentrate on analogue circuit design. In the literature, the gain reduction by the high output conductance of the transistors is discussed. In detail, we further describe gain reduction due to gate-leakage current. Finally, we present a design example of a fully differential operational amplifier in a 65 nm CMOS technology including results.

机译：在本文中，我们讨论了对电路设计者来说至关重要的新型纳米CMOS技术的特性。因此，我们专注于模拟电路设计。在文献中，讨论了由于晶体管的高输出电导导致的增益降低。详细地，我们进一步描述了由于栅极漏电流导致的增益降低。最后，我们给出了采用65 nm CMOS技术的全差分运算放大器的设计实例，包括结果。

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来源
《International journal of circuit theory and applications》 |2007年第3期|343-354|共12页
作者
Franz Schloegl; Horst Zimmermann;
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作者单位

Institute of Electrical Measurements and Circuit Design, Vienna University of Technology, Gusshausstrasse 25/354, Vienna 1040, Austria;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《化学文摘》(CA);
原文格式 PDF
正文语种 eng
中图分类电工技术;
关键词
nanometer CMOS; gate leakage; tunnelling currents; operational amplifier; cascodes; gain boost; common-mode control;

机译：纳米CMOS;栅极泄漏;隧道电流;运算放大器;级联;增强共模控制;

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5. Improvements in biasing, compensation and design methods of CMOS operational amplifiers. [D] . Nicolson, Sean T. 2004

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A design example of a 65 nm CMOS operational amplifier

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